[llvm] r306112 - AMDGPU/GlobalISel: Mark 32-bit G_AND as legal

[Tom Stellard via llvm-commits]

Author: tstellar
Date: Fri Jun 23 10:17:17 2017
New Revision: 306112

URL: http://llvm.org/viewvc/llvm-project?rev=306112&view=rev
Log:
AMDGPU/GlobalISel: Mark 32-bit G_AND as legal

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D34349

Added:
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=306112&r1=306111&r2=306112&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Fri Jun 23 10:17:17 2017
@@ -36,6 +36,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
   const LLT P2 = LLT::pointer(2, 64);
 
   setAction({G_ADD, S32}, Legal);
+  setAction({G_AND, S32}, Legal);
 
   setAction({G_BITCAST, V2S16}, Legal);
   setAction({G_BITCAST, 1, S32}, Legal);

Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir?rev=306112&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir Fri Jun 23 10:17:17 2017
@@ -0,0 +1,22 @@
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+--- |
+  define void @test_and() { ret void }
+...
+
+---
+name:            test_and
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body: |
+  bb.0:
+    liveins: %vgpr0, %vgpr1
+    ; CHECK-LABEL: name: test_and
+    ; CHECK: %2(s32) = G_AND %0, %1
+
+    %0(s32) = COPY %vgpr0
+    %1(s32) = COPY %vgpr1
+    %2(s32) = G_AND %0, %1
+...