[PATCH] D34300: [AMDGPU] simplify add x, *ext (setcc) => addc|subb x, 0, setcc

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In https://reviews.llvm.org/D34300#782899, @arsenm wrote:

> Why does this need to be a target combine? Can't we use the sub with overflow generic nodes?


Surprisingly ISD::ADDE and ISD::SUBE expect two operands, regardless of what is written in documentation. See for example this pattern with two inputs:

  let Uses = [SCC] in { // Carry in comes from SCC
  let isCommutable = 1 in {
  def S_ADDC_U32 : SOP2_32 <"s_addc_u32",
    [(set i32:$sdst, (adde (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]>;
  } // End isCommutable = 1

So I did it the same way as ARM.


Repository:
  rL LLVM

https://reviews.llvm.org/D34300