[PATCH] D34189: AMDGPU: Avoid saving/restoring reserved m0 register

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added a comment.

In https://reviews.llvm.org/D34189#780785, @MatzeB wrote:

> but you happen to hit a bug in the old scavenging code that reports SGPR4 :-/


Turns out this is not directly a bug in the register scavenger, but comes from the fact that AMDGPU creates new vregs while the scavenger is running. When the vreg to save m0 is created in the example, we have already moved past the definition of SGPR4_SGPR5 and it will miss that the register is occupied further below; It doesn't really work in this "reentrant" way.


Repository:
  rL LLVM

https://reviews.llvm.org/D34189