[PATCH] ARM: Add missing selection patterns for vnmla

[Gergö Barany via llvm-commits]

(This is my first patch to this list. Let me know if there's anything I could improve.)

For the following function:

double fn1(double d0, double d1, double d2) {
  double a = -d0 - d1 * d2;
  return a;
}

on ARM, LLVM generates code along the lines of

	vneg.f64	d0, d0
	vmls.f64	d0, d1, d2

i.e., a negate and a multiply-subtract. The attached patch adds instruction selection patterns to allow it to generate the single instruction

	vnmla.f64	d0, d1, d2

(multiply-add with negation) instead, like GCC does.
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