[PATCH] D33992: AMDGPU/GlobalISel: Mark 32-bit G_ADD as legal

[Tom Stellard via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL305232: AMDGPU/GlobalISel: Mark 32-bit G_ADD as legal (authored by tstellar).

Changed prior to commit:
  https://reviews.llvm.org/D33992?vs=101732&id=102243#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D33992

Files:
  llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir


Index: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
@@ -0,0 +1,22 @@
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+--- |
+  define void @test_add() { ret void }
+...
+
+---
+name:            test_add
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body: |
+  bb.0:
+    liveins: %vgpr0, %vgpr1
+    ; CHECK-LABEL: name: test_add
+    ; CHECK: %2(s32) = G_ADD %0, %1
+
+    %0(s32) = COPY %vgpr0
+    %1(s32) = COPY %vgpr1
+    %2(s32) = G_ADD %0, %1
+...
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -34,6 +34,8 @@
   const LLT P1 = LLT::pointer(1, 64);
   const LLT P2 = LLT::pointer(2, 64);
 
+  setAction({G_ADD, S32}, Legal);
+
   // FIXME: i1 operands to intrinsics should always be legal, but other i1
   // values may not be legal.  We need to figure out how to distinguish
   // between these two scenarios.


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