[PATCH] D19325: DAGCombine: (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 102124.
RKSimon added a comment.

Rebaing - this is part of constant canonicalizations to try and combine MUL/SHL ops separated by ADD/OR ops.

If an AMDGPU expert can check the test changes, that'd be great.


Repository:
  rL LLVM

https://reviews.llvm.org/D19325

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AMDGPU/fneg-fabs.f16.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
  test/CodeGen/AMDGPU/shl.ll
  test/CodeGen/X86/combine-shl.ll

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