[llvm] r305014 - [Hexagon] Skip mux generation when predicate register is undefined

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu Jun  8 15:56:36 2017
New Revision: 305014

URL: http://llvm.org/viewvc/llvm-project?rev=305014&view=rev
Log:
[Hexagon] Skip mux generation when predicate register is undefined

Added:
    llvm/trunk/test/CodeGen/Hexagon/mux-undef.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp?rev=305014&r1=305013&r2=305014&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp Thu Jun  8 15:56:36 2017
@@ -235,8 +235,11 @@ bool HexagonGenMux::genMuxInBlock(Machin
     unsigned DR = MI->getOperand(0).getReg();
     if (isRegPair(DR))
       continue;
+    MachineOperand &PredOp = MI->getOperand(1);
+    if (PredOp.isUndef())
+      continue;
 
-    unsigned PR = MI->getOperand(1).getReg();
+    unsigned PR = PredOp.getReg();
     unsigned Idx = I2X.lookup(MI);
     CondsetMap::iterator F = CM.find(DR);
     bool IfTrue = HII->isPredicatedTrue(Opc);

Added: llvm/trunk/test/CodeGen/Hexagon/mux-undef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/mux-undef.ll?rev=305014&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/mux-undef.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/mux-undef.ll Thu Jun  8 15:56:36 2017
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
+;
+; Make sure this test compiles successfully.
+; CHECK: jumpr r31
+
+target triple = "hexagon--elf"
+
+; Function Attrs: nounwind
+define i32 @fred() #0 {
+b0:
+  call void @foo() #0
+  br label %b1
+
+b1:                                               ; preds = %b0
+  br i1 undef, label %b2, label %b3
+
+b2:                                               ; preds = %b1
+  br label %b3
+
+b3:                                               ; preds = %b2, %b1
+  %v4 = phi i32 [ 1, %b1 ], [ 2, %b2 ]
+  ret i32 %v4
+}
+
+declare void @foo() #0
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" }