[llvm] r305004 - AMDGPU: Use correct register names in inline assembly
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 8 12:03:22 PDT 2017
Author: arsenm
Date: Thu Jun 8 14:03:20 2017
New Revision: 305004
URL: http://llvm.org/viewvc/llvm-project?rev=305004&view=rev
Log:
AMDGPU: Use correct register names in inline assembly
Fixes using physical registers in inline asm from clang.
Added:
llvm/trunk/lib/Target/AMDGPU/AMDGPURegAsmNames.inc
Modified:
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
llvm/trunk/test/CodeGen/AMDGPU/branch-relax-spill.ll
llvm/trunk/test/CodeGen/AMDGPU/exceed-max-sgprs.ll
llvm/trunk/test/CodeGen/AMDGPU/flat-scratch-reg.ll
llvm/trunk/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll
llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
llvm/trunk/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
llvm/trunk/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
llvm/trunk/test/CodeGen/AMDGPU/skip-if-dead.ll
llvm/trunk/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
llvm/trunk/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
Added: llvm/trunk/lib/Target/AMDGPU/AMDGPURegAsmNames.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegAsmNames.inc?rev=305004&view=auto
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegAsmNames.inc (added)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegAsmNames.inc Thu Jun 8 14:03:20 2017
@@ -0,0 +1,349 @@
+//===-- AMDGPURegAsmNames.inc - Register asm names ----------*- C++ -*-----===//
+
+static const char *const VGPR32RegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
+ "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
+ "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
+ "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
+ "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
+ "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
+ "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
+ "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
+ "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
+ "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
+ "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
+ "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
+ "v126", "v127", "v128", "v129", "v130", "v131", "v132", "v133", "v134",
+ "v135", "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
+ "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", "v152",
+ "v153", "v154", "v155", "v156", "v157", "v158", "v159", "v160", "v161",
+ "v162", "v163", "v164", "v165", "v166", "v167", "v168", "v169", "v170",
+ "v171", "v172", "v173", "v174", "v175", "v176", "v177", "v178", "v179",
+ "v180", "v181", "v182", "v183", "v184", "v185", "v186", "v187", "v188",
+ "v189", "v190", "v191", "v192", "v193", "v194", "v195", "v196", "v197",
+ "v198", "v199", "v200", "v201", "v202", "v203", "v204", "v205", "v206",
+ "v207", "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
+ "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", "v224",
+ "v225", "v226", "v227", "v228", "v229", "v230", "v231", "v232", "v233",
+ "v234", "v235", "v236", "v237", "v238", "v239", "v240", "v241", "v242",
+ "v243", "v244", "v245", "v246", "v247", "v248", "v249", "v250", "v251",
+ "v252", "v253", "v254", "v255"
+};
+
+static const char *const SGPR32RegNames[] = {
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9",
+ "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19",
+ "s20", "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29",
+ "s30", "s31", "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
+ "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", "s48", "s49",
+ "s50", "s51", "s52", "s53", "s54", "s55", "s56", "s57", "s58", "s59",
+ "s60", "s61", "s62", "s63", "s64", "s65", "s66", "s67", "s68", "s69",
+ "s70", "s71", "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
+ "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", "s88", "s89",
+ "s90", "s91", "s92", "s93", "s94", "s95", "s96", "s97", "s98", "s99",
+ "s100", "s101", "s102", "s103"
+};
+
+static const char *const VGPR64RegNames[] = {
+ "v[0:1]", "v[1:2]", "v[2:3]", "v[3:4]", "v[4:5]",
+ "v[5:6]", "v[6:7]", "v[7:8]", "v[8:9]", "v[9:10]",
+ "v[10:11]", "v[11:12]", "v[12:13]", "v[13:14]", "v[14:15]",
+ "v[15:16]", "v[16:17]", "v[17:18]", "v[18:19]", "v[19:20]",
+ "v[20:21]", "v[21:22]", "v[22:23]", "v[23:24]", "v[24:25]",
+ "v[25:26]", "v[26:27]", "v[27:28]", "v[28:29]", "v[29:30]",
+ "v[30:31]", "v[31:32]", "v[32:33]", "v[33:34]", "v[34:35]",
+ "v[35:36]", "v[36:37]", "v[37:38]", "v[38:39]", "v[39:40]",
+ "v[40:41]", "v[41:42]", "v[42:43]", "v[43:44]", "v[44:45]",
+ "v[45:46]", "v[46:47]", "v[47:48]", "v[48:49]", "v[49:50]",
+ "v[50:51]", "v[51:52]", "v[52:53]", "v[53:54]", "v[54:55]",
+ "v[55:56]", "v[56:57]", "v[57:58]", "v[58:59]", "v[59:60]",
+ "v[60:61]", "v[61:62]", "v[62:63]", "v[63:64]", "v[64:65]",
+ "v[65:66]", "v[66:67]", "v[67:68]", "v[68:69]", "v[69:70]",
+ "v[70:71]", "v[71:72]", "v[72:73]", "v[73:74]", "v[74:75]",
+ "v[75:76]", "v[76:77]", "v[77:78]", "v[78:79]", "v[79:80]",
+ "v[80:81]", "v[81:82]", "v[82:83]", "v[83:84]", "v[84:85]",
+ "v[85:86]", "v[86:87]", "v[87:88]", "v[88:89]", "v[89:90]",
+ "v[90:91]", "v[91:92]", "v[92:93]", "v[93:94]", "v[94:95]",
+ "v[95:96]", "v[96:97]", "v[97:98]", "v[98:99]", "v[99:100]",
+ "v[100:101]", "v[101:102]", "v[102:103]", "v[103:104]", "v[104:105]",
+ "v[105:106]", "v[106:107]", "v[107:108]", "v[108:109]", "v[109:110]",
+ "v[110:111]", "v[111:112]", "v[112:113]", "v[113:114]", "v[114:115]",
+ "v[115:116]", "v[116:117]", "v[117:118]", "v[118:119]", "v[119:120]",
+ "v[120:121]", "v[121:122]", "v[122:123]", "v[123:124]", "v[124:125]",
+ "v[125:126]", "v[126:127]", "v[127:128]", "v[128:129]", "v[129:130]",
+ "v[130:131]", "v[131:132]", "v[132:133]", "v[133:134]", "v[134:135]",
+ "v[135:136]", "v[136:137]", "v[137:138]", "v[138:139]", "v[139:140]",
+ "v[140:141]", "v[141:142]", "v[142:143]", "v[143:144]", "v[144:145]",
+ "v[145:146]", "v[146:147]", "v[147:148]", "v[148:149]", "v[149:150]",
+ "v[150:151]", "v[151:152]", "v[152:153]", "v[153:154]", "v[154:155]",
+ "v[155:156]", "v[156:157]", "v[157:158]", "v[158:159]", "v[159:160]",
+ "v[160:161]", "v[161:162]", "v[162:163]", "v[163:164]", "v[164:165]",
+ "v[165:166]", "v[166:167]", "v[167:168]", "v[168:169]", "v[169:170]",
+ "v[170:171]", "v[171:172]", "v[172:173]", "v[173:174]", "v[174:175]",
+ "v[175:176]", "v[176:177]", "v[177:178]", "v[178:179]", "v[179:180]",
+ "v[180:181]", "v[181:182]", "v[182:183]", "v[183:184]", "v[184:185]",
+ "v[185:186]", "v[186:187]", "v[187:188]", "v[188:189]", "v[189:190]",
+ "v[190:191]", "v[191:192]", "v[192:193]", "v[193:194]", "v[194:195]",
+ "v[195:196]", "v[196:197]", "v[197:198]", "v[198:199]", "v[199:200]",
+ "v[200:201]", "v[201:202]", "v[202:203]", "v[203:204]", "v[204:205]",
+ "v[205:206]", "v[206:207]", "v[207:208]", "v[208:209]", "v[209:210]",
+ "v[210:211]", "v[211:212]", "v[212:213]", "v[213:214]", "v[214:215]",
+ "v[215:216]", "v[216:217]", "v[217:218]", "v[218:219]", "v[219:220]",
+ "v[220:221]", "v[221:222]", "v[222:223]", "v[223:224]", "v[224:225]",
+ "v[225:226]", "v[226:227]", "v[227:228]", "v[228:229]", "v[229:230]",
+ "v[230:231]", "v[231:232]", "v[232:233]", "v[233:234]", "v[234:235]",
+ "v[235:236]", "v[236:237]", "v[237:238]", "v[238:239]", "v[239:240]",
+ "v[240:241]", "v[241:242]", "v[242:243]", "v[243:244]", "v[244:245]",
+ "v[245:246]", "v[246:247]", "v[247:248]", "v[248:249]", "v[249:250]",
+ "v[250:251]", "v[251:252]", "v[252:253]", "v[253:254]", "v[254:255]"
+};
+
+static const char *const VGPR96RegNames[] = {
+ "v[0:2]", "v[1:3]", "v[2:4]", "v[3:5]", "v[4:6]",
+ "v[5:7]", "v[6:8]", "v[7:9]", "v[8:10]", "v[9:11]",
+ "v[10:12]", "v[11:13]", "v[12:14]", "v[13:15]", "v[14:16]",
+ "v[15:17]", "v[16:18]", "v[17:19]", "v[18:20]", "v[19:21]",
+ "v[20:22]", "v[21:23]", "v[22:24]", "v[23:25]", "v[24:26]",
+ "v[25:27]", "v[26:28]", "v[27:29]", "v[28:30]", "v[29:31]",
+ "v[30:32]", "v[31:33]", "v[32:34]", "v[33:35]", "v[34:36]",
+ "v[35:37]", "v[36:38]", "v[37:39]", "v[38:40]", "v[39:41]",
+ "v[40:42]", "v[41:43]", "v[42:44]", "v[43:45]", "v[44:46]",
+ "v[45:47]", "v[46:48]", "v[47:49]", "v[48:50]", "v[49:51]",
+ "v[50:52]", "v[51:53]", "v[52:54]", "v[53:55]", "v[54:56]",
+ "v[55:57]", "v[56:58]", "v[57:59]", "v[58:60]", "v[59:61]",
+ "v[60:62]", "v[61:63]", "v[62:64]", "v[63:65]", "v[64:66]",
+ "v[65:67]", "v[66:68]", "v[67:69]", "v[68:70]", "v[69:71]",
+ "v[70:72]", "v[71:73]", "v[72:74]", "v[73:75]", "v[74:76]",
+ "v[75:77]", "v[76:78]", "v[77:79]", "v[78:80]", "v[79:81]",
+ "v[80:82]", "v[81:83]", "v[82:84]", "v[83:85]", "v[84:86]",
+ "v[85:87]", "v[86:88]", "v[87:89]", "v[88:90]", "v[89:91]",
+ "v[90:92]", "v[91:93]", "v[92:94]", "v[93:95]", "v[94:96]",
+ "v[95:97]", "v[96:98]", "v[97:99]", "v[98:100]", "v[99:101]",
+ "v[100:102]", "v[101:103]", "v[102:104]", "v[103:105]", "v[104:106]",
+ "v[105:107]", "v[106:108]", "v[107:109]", "v[108:110]", "v[109:111]",
+ "v[110:112]", "v[111:113]", "v[112:114]", "v[113:115]", "v[114:116]",
+ "v[115:117]", "v[116:118]", "v[117:119]", "v[118:120]", "v[119:121]",
+ "v[120:122]", "v[121:123]", "v[122:124]", "v[123:125]", "v[124:126]",
+ "v[125:127]", "v[126:128]", "v[127:129]", "v[128:130]", "v[129:131]",
+ "v[130:132]", "v[131:133]", "v[132:134]", "v[133:135]", "v[134:136]",
+ "v[135:137]", "v[136:138]", "v[137:139]", "v[138:140]", "v[139:141]",
+ "v[140:142]", "v[141:143]", "v[142:144]", "v[143:145]", "v[144:146]",
+ "v[145:147]", "v[146:148]", "v[147:149]", "v[148:150]", "v[149:151]",
+ "v[150:152]", "v[151:153]", "v[152:154]", "v[153:155]", "v[154:156]",
+ "v[155:157]", "v[156:158]", "v[157:159]", "v[158:160]", "v[159:161]",
+ "v[160:162]", "v[161:163]", "v[162:164]", "v[163:165]", "v[164:166]",
+ "v[165:167]", "v[166:168]", "v[167:169]", "v[168:170]", "v[169:171]",
+ "v[170:172]", "v[171:173]", "v[172:174]", "v[173:175]", "v[174:176]",
+ "v[175:177]", "v[176:178]", "v[177:179]", "v[178:180]", "v[179:181]",
+ "v[180:182]", "v[181:183]", "v[182:184]", "v[183:185]", "v[184:186]",
+ "v[185:187]", "v[186:188]", "v[187:189]", "v[188:190]", "v[189:191]",
+ "v[190:192]", "v[191:193]", "v[192:194]", "v[193:195]", "v[194:196]",
+ "v[195:197]", "v[196:198]", "v[197:199]", "v[198:200]", "v[199:201]",
+ "v[200:202]", "v[201:203]", "v[202:204]", "v[203:205]", "v[204:206]",
+ "v[205:207]", "v[206:208]", "v[207:209]", "v[208:210]", "v[209:211]",
+ "v[210:212]", "v[211:213]", "v[212:214]", "v[213:215]", "v[214:216]",
+ "v[215:217]", "v[216:218]", "v[217:219]", "v[218:220]", "v[219:221]",
+ "v[220:222]", "v[221:223]", "v[222:224]", "v[223:225]", "v[224:226]",
+ "v[225:227]", "v[226:228]", "v[227:229]", "v[228:230]", "v[229:231]",
+ "v[230:232]", "v[231:233]", "v[232:234]", "v[233:235]", "v[234:236]",
+ "v[235:237]", "v[236:238]", "v[237:239]", "v[238:240]", "v[239:241]",
+ "v[240:242]", "v[241:243]", "v[242:244]", "v[243:245]", "v[244:246]",
+ "v[245:247]", "v[246:248]", "v[247:249]", "v[248:250]", "v[249:251]",
+ "v[250:252]", "v[251:253]", "v[252:254]", "v[253:255]"
+};
+
+static const char *const VGPR128RegNames[] = {
+ "v[0:3]", "v[1:4]", "v[2:5]", "v[3:6]", "v[4:7]",
+ "v[5:8]", "v[6:9]", "v[7:10]", "v[8:11]", "v[9:12]",
+ "v[10:13]", "v[11:14]", "v[12:15]", "v[13:16]", "v[14:17]",
+ "v[15:18]", "v[16:19]", "v[17:20]", "v[18:21]", "v[19:22]",
+ "v[20:23]", "v[21:24]", "v[22:25]", "v[23:26]", "v[24:27]",
+ "v[25:28]", "v[26:29]", "v[27:30]", "v[28:31]", "v[29:32]",
+ "v[30:33]", "v[31:34]", "v[32:35]", "v[33:36]", "v[34:37]",
+ "v[35:38]", "v[36:39]", "v[37:40]", "v[38:41]", "v[39:42]",
+ "v[40:43]", "v[41:44]", "v[42:45]", "v[43:46]", "v[44:47]",
+ "v[45:48]", "v[46:49]", "v[47:50]", "v[48:51]", "v[49:52]",
+ "v[50:53]", "v[51:54]", "v[52:55]", "v[53:56]", "v[54:57]",
+ "v[55:58]", "v[56:59]", "v[57:60]", "v[58:61]", "v[59:62]",
+ "v[60:63]", "v[61:64]", "v[62:65]", "v[63:66]", "v[64:67]",
+ "v[65:68]", "v[66:69]", "v[67:70]", "v[68:71]", "v[69:72]",
+ "v[70:73]", "v[71:74]", "v[72:75]", "v[73:76]", "v[74:77]",
+ "v[75:78]", "v[76:79]", "v[77:80]", "v[78:81]", "v[79:82]",
+ "v[80:83]", "v[81:84]", "v[82:85]", "v[83:86]", "v[84:87]",
+ "v[85:88]", "v[86:89]", "v[87:90]", "v[88:91]", "v[89:92]",
+ "v[90:93]", "v[91:94]", "v[92:95]", "v[93:96]", "v[94:97]",
+ "v[95:98]", "v[96:99]", "v[97:100]", "v[98:101]", "v[99:102]",
+ "v[100:103]", "v[101:104]", "v[102:105]", "v[103:106]", "v[104:107]",
+ "v[105:108]", "v[106:109]", "v[107:110]", "v[108:111]", "v[109:112]",
+ "v[110:113]", "v[111:114]", "v[112:115]", "v[113:116]", "v[114:117]",
+ "v[115:118]", "v[116:119]", "v[117:120]", "v[118:121]", "v[119:122]",
+ "v[120:123]", "v[121:124]", "v[122:125]", "v[123:126]", "v[124:127]",
+ "v[125:128]", "v[126:129]", "v[127:130]", "v[128:131]", "v[129:132]",
+ "v[130:133]", "v[131:134]", "v[132:135]", "v[133:136]", "v[134:137]",
+ "v[135:138]", "v[136:139]", "v[137:140]", "v[138:141]", "v[139:142]",
+ "v[140:143]", "v[141:144]", "v[142:145]", "v[143:146]", "v[144:147]",
+ "v[145:148]", "v[146:149]", "v[147:150]", "v[148:151]", "v[149:152]",
+ "v[150:153]", "v[151:154]", "v[152:155]", "v[153:156]", "v[154:157]",
+ "v[155:158]", "v[156:159]", "v[157:160]", "v[158:161]", "v[159:162]",
+ "v[160:163]", "v[161:164]", "v[162:165]", "v[163:166]", "v[164:167]",
+ "v[165:168]", "v[166:169]", "v[167:170]", "v[168:171]", "v[169:172]",
+ "v[170:173]", "v[171:174]", "v[172:175]", "v[173:176]", "v[174:177]",
+ "v[175:178]", "v[176:179]", "v[177:180]", "v[178:181]", "v[179:182]",
+ "v[180:183]", "v[181:184]", "v[182:185]", "v[183:186]", "v[184:187]",
+ "v[185:188]", "v[186:189]", "v[187:190]", "v[188:191]", "v[189:192]",
+ "v[190:193]", "v[191:194]", "v[192:195]", "v[193:196]", "v[194:197]",
+ "v[195:198]", "v[196:199]", "v[197:200]", "v[198:201]", "v[199:202]",
+ "v[200:203]", "v[201:204]", "v[202:205]", "v[203:206]", "v[204:207]",
+ "v[205:208]", "v[206:209]", "v[207:210]", "v[208:211]", "v[209:212]",
+ "v[210:213]", "v[211:214]", "v[212:215]", "v[213:216]", "v[214:217]",
+ "v[215:218]", "v[216:219]", "v[217:220]", "v[218:221]", "v[219:222]",
+ "v[220:223]", "v[221:224]", "v[222:225]", "v[223:226]", "v[224:227]",
+ "v[225:228]", "v[226:229]", "v[227:230]", "v[228:231]", "v[229:232]",
+ "v[230:233]", "v[231:234]", "v[232:235]", "v[233:236]", "v[234:237]",
+ "v[235:238]", "v[236:239]", "v[237:240]", "v[238:241]", "v[239:242]",
+ "v[240:243]", "v[241:244]", "v[242:245]", "v[243:246]", "v[244:247]",
+ "v[245:248]", "v[246:249]", "v[247:250]", "v[248:251]", "v[249:252]",
+ "v[250:253]", "v[251:254]", "v[252:255]"
+};
+
+static const char *const VGPR256RegNames[] = {
+ "v[0:7]", "v[1:8]", "v[2:9]", "v[3:10]", "v[4:11]",
+ "v[5:12]", "v[6:13]", "v[7:14]", "v[8:15]", "v[9:16]",
+ "v[10:17]", "v[11:18]", "v[12:19]", "v[13:20]", "v[14:21]",
+ "v[15:22]", "v[16:23]", "v[17:24]", "v[18:25]", "v[19:26]",
+ "v[20:27]", "v[21:28]", "v[22:29]", "v[23:30]", "v[24:31]",
+ "v[25:32]", "v[26:33]", "v[27:34]", "v[28:35]", "v[29:36]",
+ "v[30:37]", "v[31:38]", "v[32:39]", "v[33:40]", "v[34:41]",
+ "v[35:42]", "v[36:43]", "v[37:44]", "v[38:45]", "v[39:46]",
+ "v[40:47]", "v[41:48]", "v[42:49]", "v[43:50]", "v[44:51]",
+ "v[45:52]", "v[46:53]", "v[47:54]", "v[48:55]", "v[49:56]",
+ "v[50:57]", "v[51:58]", "v[52:59]", "v[53:60]", "v[54:61]",
+ "v[55:62]", "v[56:63]", "v[57:64]", "v[58:65]", "v[59:66]",
+ "v[60:67]", "v[61:68]", "v[62:69]", "v[63:70]", "v[64:71]",
+ "v[65:72]", "v[66:73]", "v[67:74]", "v[68:75]", "v[69:76]",
+ "v[70:77]", "v[71:78]", "v[72:79]", "v[73:80]", "v[74:81]",
+ "v[75:82]", "v[76:83]", "v[77:84]", "v[78:85]", "v[79:86]",
+ "v[80:87]", "v[81:88]", "v[82:89]", "v[83:90]", "v[84:91]",
+ "v[85:92]", "v[86:93]", "v[87:94]", "v[88:95]", "v[89:96]",
+ "v[90:97]", "v[91:98]", "v[92:99]", "v[93:100]", "v[94:101]",
+ "v[95:102]", "v[96:103]", "v[97:104]", "v[98:105]", "v[99:106]",
+ "v[100:107]", "v[101:108]", "v[102:109]", "v[103:110]", "v[104:111]",
+ "v[105:112]", "v[106:113]", "v[107:114]", "v[108:115]", "v[109:116]",
+ "v[110:117]", "v[111:118]", "v[112:119]", "v[113:120]", "v[114:121]",
+ "v[115:122]", "v[116:123]", "v[117:124]", "v[118:125]", "v[119:126]",
+ "v[120:127]", "v[121:128]", "v[122:129]", "v[123:130]", "v[124:131]",
+ "v[125:132]", "v[126:133]", "v[127:134]", "v[128:135]", "v[129:136]",
+ "v[130:137]", "v[131:138]", "v[132:139]", "v[133:140]", "v[134:141]",
+ "v[135:142]", "v[136:143]", "v[137:144]", "v[138:145]", "v[139:146]",
+ "v[140:147]", "v[141:148]", "v[142:149]", "v[143:150]", "v[144:151]",
+ "v[145:152]", "v[146:153]", "v[147:154]", "v[148:155]", "v[149:156]",
+ "v[150:157]", "v[151:158]", "v[152:159]", "v[153:160]", "v[154:161]",
+ "v[155:162]", "v[156:163]", "v[157:164]", "v[158:165]", "v[159:166]",
+ "v[160:167]", "v[161:168]", "v[162:169]", "v[163:170]", "v[164:171]",
+ "v[165:172]", "v[166:173]", "v[167:174]", "v[168:175]", "v[169:176]",
+ "v[170:177]", "v[171:178]", "v[172:179]", "v[173:180]", "v[174:181]",
+ "v[175:182]", "v[176:183]", "v[177:184]", "v[178:185]", "v[179:186]",
+ "v[180:187]", "v[181:188]", "v[182:189]", "v[183:190]", "v[184:191]",
+ "v[185:192]", "v[186:193]", "v[187:194]", "v[188:195]", "v[189:196]",
+ "v[190:197]", "v[191:198]", "v[192:199]", "v[193:200]", "v[194:201]",
+ "v[195:202]", "v[196:203]", "v[197:204]", "v[198:205]", "v[199:206]",
+ "v[200:207]", "v[201:208]", "v[202:209]", "v[203:210]", "v[204:211]",
+ "v[205:212]", "v[206:213]", "v[207:214]", "v[208:215]", "v[209:216]",
+ "v[210:217]", "v[211:218]", "v[212:219]", "v[213:220]", "v[214:221]",
+ "v[215:222]", "v[216:223]", "v[217:224]", "v[218:225]", "v[219:226]",
+ "v[220:227]", "v[221:228]", "v[222:229]", "v[223:230]", "v[224:231]",
+ "v[225:232]", "v[226:233]", "v[227:234]", "v[228:235]", "v[229:236]",
+ "v[230:237]", "v[231:238]", "v[232:239]", "v[233:240]", "v[234:241]",
+ "v[235:242]", "v[236:243]", "v[237:244]", "v[238:245]", "v[239:246]",
+ "v[240:247]", "v[241:248]", "v[242:249]", "v[243:250]", "v[244:251]",
+ "v[245:252]", "v[246:253]", "v[247:254]", "v[248:255]"
+};
+
+static const char *const VGPR512RegNames[] = {
+ "v[0:15]", "v[1:16]", "v[2:17]", "v[3:18]", "v[4:19]",
+ "v[5:20]", "v[6:21]", "v[7:22]", "v[8:23]", "v[9:24]",
+ "v[10:25]", "v[11:26]", "v[12:27]", "v[13:28]", "v[14:29]",
+ "v[15:30]", "v[16:31]", "v[17:32]", "v[18:33]", "v[19:34]",
+ "v[20:35]", "v[21:36]", "v[22:37]", "v[23:38]", "v[24:39]",
+ "v[25:40]", "v[26:41]", "v[27:42]", "v[28:43]", "v[29:44]",
+ "v[30:45]", "v[31:46]", "v[32:47]", "v[33:48]", "v[34:49]",
+ "v[35:50]", "v[36:51]", "v[37:52]", "v[38:53]", "v[39:54]",
+ "v[40:55]", "v[41:56]", "v[42:57]", "v[43:58]", "v[44:59]",
+ "v[45:60]", "v[46:61]", "v[47:62]", "v[48:63]", "v[49:64]",
+ "v[50:65]", "v[51:66]", "v[52:67]", "v[53:68]", "v[54:69]",
+ "v[55:70]", "v[56:71]", "v[57:72]", "v[58:73]", "v[59:74]",
+ "v[60:75]", "v[61:76]", "v[62:77]", "v[63:78]", "v[64:79]",
+ "v[65:80]", "v[66:81]", "v[67:82]", "v[68:83]", "v[69:84]",
+ "v[70:85]", "v[71:86]", "v[72:87]", "v[73:88]", "v[74:89]",
+ "v[75:90]", "v[76:91]", "v[77:92]", "v[78:93]", "v[79:94]",
+ "v[80:95]", "v[81:96]", "v[82:97]", "v[83:98]", "v[84:99]",
+ "v[85:100]", "v[86:101]", "v[87:102]", "v[88:103]", "v[89:104]",
+ "v[90:105]", "v[91:106]", "v[92:107]", "v[93:108]", "v[94:109]",
+ "v[95:110]", "v[96:111]", "v[97:112]", "v[98:113]", "v[99:114]",
+ "v[100:115]", "v[101:116]", "v[102:117]", "v[103:118]", "v[104:119]",
+ "v[105:120]", "v[106:121]", "v[107:122]", "v[108:123]", "v[109:124]",
+ "v[110:125]", "v[111:126]", "v[112:127]", "v[113:128]", "v[114:129]",
+ "v[115:130]", "v[116:131]", "v[117:132]", "v[118:133]", "v[119:134]",
+ "v[120:135]", "v[121:136]", "v[122:137]", "v[123:138]", "v[124:139]",
+ "v[125:140]", "v[126:141]", "v[127:142]", "v[128:143]", "v[129:144]",
+ "v[130:145]", "v[131:146]", "v[132:147]", "v[133:148]", "v[134:149]",
+ "v[135:150]", "v[136:151]", "v[137:152]", "v[138:153]", "v[139:154]",
+ "v[140:155]", "v[141:156]", "v[142:157]", "v[143:158]", "v[144:159]",
+ "v[145:160]", "v[146:161]", "v[147:162]", "v[148:163]", "v[149:164]",
+ "v[150:165]", "v[151:166]", "v[152:167]", "v[153:168]", "v[154:169]",
+ "v[155:170]", "v[156:171]", "v[157:172]", "v[158:173]", "v[159:174]",
+ "v[160:175]", "v[161:176]", "v[162:177]", "v[163:178]", "v[164:179]",
+ "v[165:180]", "v[166:181]", "v[167:182]", "v[168:183]", "v[169:184]",
+ "v[170:185]", "v[171:186]", "v[172:187]", "v[173:188]", "v[174:189]",
+ "v[175:190]", "v[176:191]", "v[177:192]", "v[178:193]", "v[179:194]",
+ "v[180:195]", "v[181:196]", "v[182:197]", "v[183:198]", "v[184:199]",
+ "v[185:200]", "v[186:201]", "v[187:202]", "v[188:203]", "v[189:204]",
+ "v[190:205]", "v[191:206]", "v[192:207]", "v[193:208]", "v[194:209]",
+ "v[195:210]", "v[196:211]", "v[197:212]", "v[198:213]", "v[199:214]",
+ "v[200:215]", "v[201:216]", "v[202:217]", "v[203:218]", "v[204:219]",
+ "v[205:220]", "v[206:221]", "v[207:222]", "v[208:223]", "v[209:224]",
+ "v[210:225]", "v[211:226]", "v[212:227]", "v[213:228]", "v[214:229]",
+ "v[215:230]", "v[216:231]", "v[217:232]", "v[218:233]", "v[219:234]",
+ "v[220:235]", "v[221:236]", "v[222:237]", "v[223:238]", "v[224:239]",
+ "v[225:240]", "v[226:241]", "v[227:242]", "v[228:243]", "v[229:244]",
+ "v[230:245]", "v[231:246]", "v[232:247]", "v[233:248]", "v[234:249]",
+ "v[235:250]", "v[236:251]", "v[237:252]", "v[238:253]", "v[239:254]",
+ "v[240:255]"
+};
+
+static const char *const SGPR64RegNames[] = {
+ "s[0:1]", "s[2:3]", "s[4:5]", "s[6:7]", "s[8:9]", "s[10:11]",
+ "s[12:13]", "s[14:15]", "s[16:17]", "s[18:19]", "s[20:21]", "s[22:23]",
+ "s[24:25]", "s[26:27]", "s[28:29]", "s[30:31]", "s[32:33]", "s[34:35]",
+ "s[36:37]", "s[38:39]", "s[40:41]", "s[42:43]", "s[44:45]", "s[46:47]",
+ "s[48:49]", "s[50:51]", "s[52:53]", "s[54:55]", "s[56:57]", "s[58:59]",
+ "s[60:61]", "s[62:63]", "s[64:65]", "s[66:67]", "s[68:69]", "s[70:71]",
+ "s[72:73]", "s[74:75]", "s[76:77]", "s[78:79]", "s[80:81]", "s[82:83]",
+ "s[84:85]", "s[86:87]", "s[88:89]", "s[90:91]", "s[92:93]", "s[94:95]",
+ "s[96:97]", "s[98:99]", "s[100:101]", "s[102:103]"
+};
+
+static const char *const SGPR128RegNames[] = {
+ "s[0:3]", "s[4:7]", "s[8:11]", "s[12:15]", "s[16:19]", "s[20:23]",
+ "s[24:27]", "s[28:31]", "s[32:35]", "s[36:39]", "s[40:43]", "s[44:47]",
+ "s[48:51]", "s[52:55]", "s[56:59]", "s[60:63]", "s[64:67]", "s[68:71]",
+ "s[72:75]", "s[76:79]", "s[80:83]", "s[84:87]", "s[88:91]", "s[92:95]",
+ "s[96:99]", "s[100:103]"
+};
+
+static const char *const SGPR256RegNames[] = {
+ "s[0:7]", "s[4:11]", "s[8:15]", "s[12:19]", "s[16:23]",
+ "s[20:27]", "s[24:31]", "s[28:35]", "s[32:39]", "s[36:43]",
+ "s[40:47]", "s[44:51]", "s[48:55]", "s[52:59]", "s[56:63]",
+ "s[60:67]", "s[64:71]", "s[68:75]", "s[72:79]", "s[76:83]",
+ "s[80:87]", "s[84:91]", "s[88:95]", "s[92:99]", "s[96:103]"
+};
+
+static const char *const SGPR512RegNames[] = {
+ "s[0:15]", "s[4:19]", "s[8:23]", "s[12:27]", "s[16:31]", "s[20:35]",
+ "s[24:39]", "s[28:43]", "s[32:47]", "s[36:51]", "s[40:55]", "s[44:59]",
+ "s[48:63]", "s[52:67]", "s[56:71]", "s[60:75]", "s[64:79]", "s[68:83]",
+ "s[72:87]", "s[76:91]", "s[80:95]", "s[84:99]", "s[88:103]"
+};
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Thu Jun 8 14:03:20 2017
@@ -1104,6 +1104,65 @@ void SIRegisterInfo::eliminateFrameIndex
}
}
+StringRef SIRegisterInfo::getRegAsmName(unsigned Reg) const {
+ #include "AMDGPURegAsmNames.inc"
+
+ #define REG_RANGE(BeginReg, EndReg, RegTable) \
+ if (Reg >= BeginReg && Reg <= EndReg) { \
+ unsigned Index = Reg - BeginReg; \
+ assert(Index < array_lengthof(RegTable)); \
+ return RegTable[Index]; \
+ }
+
+ REG_RANGE(AMDGPU::VGPR0, AMDGPU::VGPR255, VGPR32RegNames);
+ REG_RANGE(AMDGPU::SGPR0, AMDGPU::SGPR103, SGPR32RegNames);
+ REG_RANGE(AMDGPU::VGPR0_VGPR1, AMDGPU::VGPR254_VGPR255, VGPR64RegNames);
+ REG_RANGE(AMDGPU::SGPR0_SGPR1, AMDGPU::SGPR102_SGPR103, SGPR64RegNames);
+ REG_RANGE(AMDGPU::VGPR0_VGPR1_VGPR2, AMDGPU::VGPR253_VGPR254_VGPR255,
+ VGPR96RegNames);
+
+ REG_RANGE(AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3,
+ AMDGPU::VGPR252_VGPR253_VGPR254_VGPR255,
+ VGPR128RegNames);
+ REG_RANGE(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3,
+ AMDGPU::SGPR100_SGPR101_SGPR102_SGPR103,
+ SGPR128RegNames);
+
+ REG_RANGE(AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7,
+ AMDGPU::VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255,
+ VGPR256RegNames);
+
+ REG_RANGE(
+ AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15,
+ AMDGPU::VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255,
+ VGPR512RegNames);
+
+ REG_RANGE(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7,
+ AMDGPU::SGPR96_SGPR97_SGPR98_SGPR99_SGPR100_SGPR101_SGPR102_SGPR103,
+ SGPR256RegNames);
+
+ REG_RANGE(
+ AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15,
+ AMDGPU::SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95_SGPR96_SGPR97_SGPR98_SGPR99_SGPR100_SGPR101_SGPR102_SGPR103,
+ SGPR512RegNames
+ );
+
+#undef REG_RANGE
+
+ // FIXME: Rename flat_scr so we don't need to special case this.
+ switch (Reg) {
+ case AMDGPU::FLAT_SCR:
+ return "flat_scratch";
+ case AMDGPU::FLAT_SCR_LO:
+ return "flat_scratch_lo";
+ case AMDGPU::FLAT_SCR_HI:
+ return "flat_scratch_hi";
+ default:
+ // For the special named registers the default is fine.
+ return TargetRegisterInfo::getRegAsmName(Reg);
+ }
+}
+
// FIXME: This is very slow. It might be worth creating a map from physreg to
// register class.
const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h Thu Jun 8 14:03:20 2017
@@ -118,6 +118,8 @@ public:
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI,
int FI, RegScavenger *RS) const;
+ StringRef getRegAsmName(unsigned Reg) const override;
+
unsigned getHWRegIndex(unsigned Reg) const {
return getEncodingValue(Reg) & 0xff;
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/branch-relax-spill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/branch-relax-spill.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/branch-relax-spill.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/branch-relax-spill.ll Thu Jun 8 14:03:20 2017
@@ -7,110 +7,110 @@
define amdgpu_kernel void @spill(i32 addrspace(1)* %arg, i32 %cnd) #0 {
entry:
- %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={SGPR0}"() #0
- %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={SGPR1}"() #0
- %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={SGPR2}"() #0
- %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={SGPR3}"() #0
- %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={SGPR4}"() #0
- %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={SGPR5}"() #0
- %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={SGPR6}"() #0
- %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={SGPR7}"() #0
- %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={SGPR8}"() #0
- %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={SGPR9}"() #0
- %sgpr10 = tail call i32 asm sideeffect "s_mov_b32 s10, 0", "={SGPR10}"() #0
- %sgpr11 = tail call i32 asm sideeffect "s_mov_b32 s11, 0", "={SGPR11}"() #0
- %sgpr12 = tail call i32 asm sideeffect "s_mov_b32 s12, 0", "={SGPR12}"() #0
- %sgpr13 = tail call i32 asm sideeffect "s_mov_b32 s13, 0", "={SGPR13}"() #0
- %sgpr14 = tail call i32 asm sideeffect "s_mov_b32 s14, 0", "={SGPR14}"() #0
- %sgpr15 = tail call i32 asm sideeffect "s_mov_b32 s15, 0", "={SGPR15}"() #0
- %sgpr16 = tail call i32 asm sideeffect "s_mov_b32 s16, 0", "={SGPR16}"() #0
- %sgpr17 = tail call i32 asm sideeffect "s_mov_b32 s17, 0", "={SGPR17}"() #0
- %sgpr18 = tail call i32 asm sideeffect "s_mov_b32 s18, 0", "={SGPR18}"() #0
- %sgpr19 = tail call i32 asm sideeffect "s_mov_b32 s19, 0", "={SGPR19}"() #0
- %sgpr20 = tail call i32 asm sideeffect "s_mov_b32 s20, 0", "={SGPR20}"() #0
- %sgpr21 = tail call i32 asm sideeffect "s_mov_b32 s21, 0", "={SGPR21}"() #0
- %sgpr22 = tail call i32 asm sideeffect "s_mov_b32 s22, 0", "={SGPR22}"() #0
- %sgpr23 = tail call i32 asm sideeffect "s_mov_b32 s23, 0", "={SGPR23}"() #0
- %sgpr24 = tail call i32 asm sideeffect "s_mov_b32 s24, 0", "={SGPR24}"() #0
- %sgpr25 = tail call i32 asm sideeffect "s_mov_b32 s25, 0", "={SGPR25}"() #0
- %sgpr26 = tail call i32 asm sideeffect "s_mov_b32 s26, 0", "={SGPR26}"() #0
- %sgpr27 = tail call i32 asm sideeffect "s_mov_b32 s27, 0", "={SGPR27}"() #0
- %sgpr28 = tail call i32 asm sideeffect "s_mov_b32 s28, 0", "={SGPR28}"() #0
- %sgpr29 = tail call i32 asm sideeffect "s_mov_b32 s29, 0", "={SGPR29}"() #0
- %sgpr30 = tail call i32 asm sideeffect "s_mov_b32 s30, 0", "={SGPR30}"() #0
- %sgpr31 = tail call i32 asm sideeffect "s_mov_b32 s31, 0", "={SGPR31}"() #0
- %sgpr32 = tail call i32 asm sideeffect "s_mov_b32 s32, 0", "={SGPR32}"() #0
- %sgpr33 = tail call i32 asm sideeffect "s_mov_b32 s33, 0", "={SGPR33}"() #0
- %sgpr34 = tail call i32 asm sideeffect "s_mov_b32 s34, 0", "={SGPR34}"() #0
- %sgpr35 = tail call i32 asm sideeffect "s_mov_b32 s35, 0", "={SGPR35}"() #0
- %sgpr36 = tail call i32 asm sideeffect "s_mov_b32 s36, 0", "={SGPR36}"() #0
- %sgpr37 = tail call i32 asm sideeffect "s_mov_b32 s37, 0", "={SGPR37}"() #0
- %sgpr38 = tail call i32 asm sideeffect "s_mov_b32 s38, 0", "={SGPR38}"() #0
- %sgpr39 = tail call i32 asm sideeffect "s_mov_b32 s39, 0", "={SGPR39}"() #0
- %sgpr40 = tail call i32 asm sideeffect "s_mov_b32 s40, 0", "={SGPR40}"() #0
- %sgpr41 = tail call i32 asm sideeffect "s_mov_b32 s41, 0", "={SGPR41}"() #0
- %sgpr42 = tail call i32 asm sideeffect "s_mov_b32 s42, 0", "={SGPR42}"() #0
- %sgpr43 = tail call i32 asm sideeffect "s_mov_b32 s43, 0", "={SGPR43}"() #0
- %sgpr44 = tail call i32 asm sideeffect "s_mov_b32 s44, 0", "={SGPR44}"() #0
- %sgpr45 = tail call i32 asm sideeffect "s_mov_b32 s45, 0", "={SGPR45}"() #0
- %sgpr46 = tail call i32 asm sideeffect "s_mov_b32 s46, 0", "={SGPR46}"() #0
- %sgpr47 = tail call i32 asm sideeffect "s_mov_b32 s47, 0", "={SGPR47}"() #0
- %sgpr48 = tail call i32 asm sideeffect "s_mov_b32 s48, 0", "={SGPR48}"() #0
- %sgpr49 = tail call i32 asm sideeffect "s_mov_b32 s49, 0", "={SGPR49}"() #0
- %sgpr50 = tail call i32 asm sideeffect "s_mov_b32 s50, 0", "={SGPR50}"() #0
- %sgpr51 = tail call i32 asm sideeffect "s_mov_b32 s51, 0", "={SGPR51}"() #0
- %sgpr52 = tail call i32 asm sideeffect "s_mov_b32 s52, 0", "={SGPR52}"() #0
- %sgpr53 = tail call i32 asm sideeffect "s_mov_b32 s53, 0", "={SGPR53}"() #0
- %sgpr54 = tail call i32 asm sideeffect "s_mov_b32 s54, 0", "={SGPR54}"() #0
- %sgpr55 = tail call i32 asm sideeffect "s_mov_b32 s55, 0", "={SGPR55}"() #0
- %sgpr56 = tail call i32 asm sideeffect "s_mov_b32 s56, 0", "={SGPR56}"() #0
- %sgpr57 = tail call i32 asm sideeffect "s_mov_b32 s57, 0", "={SGPR57}"() #0
- %sgpr58 = tail call i32 asm sideeffect "s_mov_b32 s58, 0", "={SGPR58}"() #0
- %sgpr59 = tail call i32 asm sideeffect "s_mov_b32 s59, 0", "={SGPR59}"() #0
- %sgpr60 = tail call i32 asm sideeffect "s_mov_b32 s60, 0", "={SGPR60}"() #0
- %sgpr61 = tail call i32 asm sideeffect "s_mov_b32 s61, 0", "={SGPR61}"() #0
- %sgpr62 = tail call i32 asm sideeffect "s_mov_b32 s62, 0", "={SGPR62}"() #0
- %sgpr63 = tail call i32 asm sideeffect "s_mov_b32 s63, 0", "={SGPR63}"() #0
- %sgpr64 = tail call i32 asm sideeffect "s_mov_b32 s64, 0", "={SGPR64}"() #0
- %sgpr65 = tail call i32 asm sideeffect "s_mov_b32 s65, 0", "={SGPR65}"() #0
- %sgpr66 = tail call i32 asm sideeffect "s_mov_b32 s66, 0", "={SGPR66}"() #0
- %sgpr67 = tail call i32 asm sideeffect "s_mov_b32 s67, 0", "={SGPR67}"() #0
- %sgpr68 = tail call i32 asm sideeffect "s_mov_b32 s68, 0", "={SGPR68}"() #0
- %sgpr69 = tail call i32 asm sideeffect "s_mov_b32 s69, 0", "={SGPR69}"() #0
- %sgpr70 = tail call i32 asm sideeffect "s_mov_b32 s70, 0", "={SGPR70}"() #0
- %sgpr71 = tail call i32 asm sideeffect "s_mov_b32 s71, 0", "={SGPR71}"() #0
- %sgpr72 = tail call i32 asm sideeffect "s_mov_b32 s72, 0", "={SGPR72}"() #0
- %sgpr73 = tail call i32 asm sideeffect "s_mov_b32 s73, 0", "={SGPR73}"() #0
- %sgpr74 = tail call i32 asm sideeffect "s_mov_b32 s74, 0", "={SGPR74}"() #0
- %sgpr75 = tail call i32 asm sideeffect "s_mov_b32 s75, 0", "={SGPR75}"() #0
- %sgpr76 = tail call i32 asm sideeffect "s_mov_b32 s76, 0", "={SGPR76}"() #0
- %sgpr77 = tail call i32 asm sideeffect "s_mov_b32 s77, 0", "={SGPR77}"() #0
- %sgpr78 = tail call i32 asm sideeffect "s_mov_b32 s78, 0", "={SGPR78}"() #0
- %sgpr79 = tail call i32 asm sideeffect "s_mov_b32 s79, 0", "={SGPR79}"() #0
- %sgpr80 = tail call i32 asm sideeffect "s_mov_b32 s80, 0", "={SGPR80}"() #0
- %sgpr81 = tail call i32 asm sideeffect "s_mov_b32 s81, 0", "={SGPR81}"() #0
- %sgpr82 = tail call i32 asm sideeffect "s_mov_b32 s82, 0", "={SGPR82}"() #0
- %sgpr83 = tail call i32 asm sideeffect "s_mov_b32 s83, 0", "={SGPR83}"() #0
- %sgpr84 = tail call i32 asm sideeffect "s_mov_b32 s84, 0", "={SGPR84}"() #0
- %sgpr85 = tail call i32 asm sideeffect "s_mov_b32 s85, 0", "={SGPR85}"() #0
- %sgpr86 = tail call i32 asm sideeffect "s_mov_b32 s86, 0", "={SGPR86}"() #0
- %sgpr87 = tail call i32 asm sideeffect "s_mov_b32 s87, 0", "={SGPR87}"() #0
- %sgpr88 = tail call i32 asm sideeffect "s_mov_b32 s88, 0", "={SGPR88}"() #0
- %sgpr89 = tail call i32 asm sideeffect "s_mov_b32 s89, 0", "={SGPR89}"() #0
- %sgpr90 = tail call i32 asm sideeffect "s_mov_b32 s90, 0", "={SGPR90}"() #0
- %sgpr91 = tail call i32 asm sideeffect "s_mov_b32 s91, 0", "={SGPR91}"() #0
- %sgpr92 = tail call i32 asm sideeffect "s_mov_b32 s92, 0", "={SGPR92}"() #0
- %sgpr93 = tail call i32 asm sideeffect "s_mov_b32 s93, 0", "={SGPR93}"() #0
- %sgpr94 = tail call i32 asm sideeffect "s_mov_b32 s94, 0", "={SGPR94}"() #0
- %sgpr95 = tail call i32 asm sideeffect "s_mov_b32 s95, 0", "={SGPR95}"() #0
- %sgpr96 = tail call i32 asm sideeffect "s_mov_b32 s96, 0", "={SGPR96}"() #0
- %sgpr97 = tail call i32 asm sideeffect "s_mov_b32 s97, 0", "={SGPR97}"() #0
- %sgpr98 = tail call i32 asm sideeffect "s_mov_b32 s98, 0", "={SGPR98}"() #0
- %sgpr99 = tail call i32 asm sideeffect "s_mov_b32 s99, 0", "={SGPR99}"() #0
- %sgpr100 = tail call i32 asm sideeffect "s_mov_b32 s100, 0", "={SGPR100}"() #0
- %sgpr101 = tail call i32 asm sideeffect "s_mov_b32 s101, 0", "={SGPR101}"() #0
- %sgpr102 = tail call i32 asm sideeffect "s_mov_b32 s102, 0", "={SGPR102}"() #0
- %sgpr103 = tail call i32 asm sideeffect "s_mov_b32 s103, 0", "={SGPR103}"() #0
+ %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
+ %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
+ %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
+ %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
+ %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
+ %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
+ %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
+ %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
+ %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
+ %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
+ %sgpr10 = tail call i32 asm sideeffect "s_mov_b32 s10, 0", "={s10}"() #0
+ %sgpr11 = tail call i32 asm sideeffect "s_mov_b32 s11, 0", "={s11}"() #0
+ %sgpr12 = tail call i32 asm sideeffect "s_mov_b32 s12, 0", "={s12}"() #0
+ %sgpr13 = tail call i32 asm sideeffect "s_mov_b32 s13, 0", "={s13}"() #0
+ %sgpr14 = tail call i32 asm sideeffect "s_mov_b32 s14, 0", "={s14}"() #0
+ %sgpr15 = tail call i32 asm sideeffect "s_mov_b32 s15, 0", "={s15}"() #0
+ %sgpr16 = tail call i32 asm sideeffect "s_mov_b32 s16, 0", "={s16}"() #0
+ %sgpr17 = tail call i32 asm sideeffect "s_mov_b32 s17, 0", "={s17}"() #0
+ %sgpr18 = tail call i32 asm sideeffect "s_mov_b32 s18, 0", "={s18}"() #0
+ %sgpr19 = tail call i32 asm sideeffect "s_mov_b32 s19, 0", "={s19}"() #0
+ %sgpr20 = tail call i32 asm sideeffect "s_mov_b32 s20, 0", "={s20}"() #0
+ %sgpr21 = tail call i32 asm sideeffect "s_mov_b32 s21, 0", "={s21}"() #0
+ %sgpr22 = tail call i32 asm sideeffect "s_mov_b32 s22, 0", "={s22}"() #0
+ %sgpr23 = tail call i32 asm sideeffect "s_mov_b32 s23, 0", "={s23}"() #0
+ %sgpr24 = tail call i32 asm sideeffect "s_mov_b32 s24, 0", "={s24}"() #0
+ %sgpr25 = tail call i32 asm sideeffect "s_mov_b32 s25, 0", "={s25}"() #0
+ %sgpr26 = tail call i32 asm sideeffect "s_mov_b32 s26, 0", "={s26}"() #0
+ %sgpr27 = tail call i32 asm sideeffect "s_mov_b32 s27, 0", "={s27}"() #0
+ %sgpr28 = tail call i32 asm sideeffect "s_mov_b32 s28, 0", "={s28}"() #0
+ %sgpr29 = tail call i32 asm sideeffect "s_mov_b32 s29, 0", "={s29}"() #0
+ %sgpr30 = tail call i32 asm sideeffect "s_mov_b32 s30, 0", "={s30}"() #0
+ %sgpr31 = tail call i32 asm sideeffect "s_mov_b32 s31, 0", "={s31}"() #0
+ %sgpr32 = tail call i32 asm sideeffect "s_mov_b32 s32, 0", "={s32}"() #0
+ %sgpr33 = tail call i32 asm sideeffect "s_mov_b32 s33, 0", "={s33}"() #0
+ %sgpr34 = tail call i32 asm sideeffect "s_mov_b32 s34, 0", "={s34}"() #0
+ %sgpr35 = tail call i32 asm sideeffect "s_mov_b32 s35, 0", "={s35}"() #0
+ %sgpr36 = tail call i32 asm sideeffect "s_mov_b32 s36, 0", "={s36}"() #0
+ %sgpr37 = tail call i32 asm sideeffect "s_mov_b32 s37, 0", "={s37}"() #0
+ %sgpr38 = tail call i32 asm sideeffect "s_mov_b32 s38, 0", "={s38}"() #0
+ %sgpr39 = tail call i32 asm sideeffect "s_mov_b32 s39, 0", "={s39}"() #0
+ %sgpr40 = tail call i32 asm sideeffect "s_mov_b32 s40, 0", "={s40}"() #0
+ %sgpr41 = tail call i32 asm sideeffect "s_mov_b32 s41, 0", "={s41}"() #0
+ %sgpr42 = tail call i32 asm sideeffect "s_mov_b32 s42, 0", "={s42}"() #0
+ %sgpr43 = tail call i32 asm sideeffect "s_mov_b32 s43, 0", "={s43}"() #0
+ %sgpr44 = tail call i32 asm sideeffect "s_mov_b32 s44, 0", "={s44}"() #0
+ %sgpr45 = tail call i32 asm sideeffect "s_mov_b32 s45, 0", "={s45}"() #0
+ %sgpr46 = tail call i32 asm sideeffect "s_mov_b32 s46, 0", "={s46}"() #0
+ %sgpr47 = tail call i32 asm sideeffect "s_mov_b32 s47, 0", "={s47}"() #0
+ %sgpr48 = tail call i32 asm sideeffect "s_mov_b32 s48, 0", "={s48}"() #0
+ %sgpr49 = tail call i32 asm sideeffect "s_mov_b32 s49, 0", "={s49}"() #0
+ %sgpr50 = tail call i32 asm sideeffect "s_mov_b32 s50, 0", "={s50}"() #0
+ %sgpr51 = tail call i32 asm sideeffect "s_mov_b32 s51, 0", "={s51}"() #0
+ %sgpr52 = tail call i32 asm sideeffect "s_mov_b32 s52, 0", "={s52}"() #0
+ %sgpr53 = tail call i32 asm sideeffect "s_mov_b32 s53, 0", "={s53}"() #0
+ %sgpr54 = tail call i32 asm sideeffect "s_mov_b32 s54, 0", "={s54}"() #0
+ %sgpr55 = tail call i32 asm sideeffect "s_mov_b32 s55, 0", "={s55}"() #0
+ %sgpr56 = tail call i32 asm sideeffect "s_mov_b32 s56, 0", "={s56}"() #0
+ %sgpr57 = tail call i32 asm sideeffect "s_mov_b32 s57, 0", "={s57}"() #0
+ %sgpr58 = tail call i32 asm sideeffect "s_mov_b32 s58, 0", "={s58}"() #0
+ %sgpr59 = tail call i32 asm sideeffect "s_mov_b32 s59, 0", "={s59}"() #0
+ %sgpr60 = tail call i32 asm sideeffect "s_mov_b32 s60, 0", "={s60}"() #0
+ %sgpr61 = tail call i32 asm sideeffect "s_mov_b32 s61, 0", "={s61}"() #0
+ %sgpr62 = tail call i32 asm sideeffect "s_mov_b32 s62, 0", "={s62}"() #0
+ %sgpr63 = tail call i32 asm sideeffect "s_mov_b32 s63, 0", "={s63}"() #0
+ %sgpr64 = tail call i32 asm sideeffect "s_mov_b32 s64, 0", "={s64}"() #0
+ %sgpr65 = tail call i32 asm sideeffect "s_mov_b32 s65, 0", "={s65}"() #0
+ %sgpr66 = tail call i32 asm sideeffect "s_mov_b32 s66, 0", "={s66}"() #0
+ %sgpr67 = tail call i32 asm sideeffect "s_mov_b32 s67, 0", "={s67}"() #0
+ %sgpr68 = tail call i32 asm sideeffect "s_mov_b32 s68, 0", "={s68}"() #0
+ %sgpr69 = tail call i32 asm sideeffect "s_mov_b32 s69, 0", "={s69}"() #0
+ %sgpr70 = tail call i32 asm sideeffect "s_mov_b32 s70, 0", "={s70}"() #0
+ %sgpr71 = tail call i32 asm sideeffect "s_mov_b32 s71, 0", "={s71}"() #0
+ %sgpr72 = tail call i32 asm sideeffect "s_mov_b32 s72, 0", "={s72}"() #0
+ %sgpr73 = tail call i32 asm sideeffect "s_mov_b32 s73, 0", "={s73}"() #0
+ %sgpr74 = tail call i32 asm sideeffect "s_mov_b32 s74, 0", "={s74}"() #0
+ %sgpr75 = tail call i32 asm sideeffect "s_mov_b32 s75, 0", "={s75}"() #0
+ %sgpr76 = tail call i32 asm sideeffect "s_mov_b32 s76, 0", "={s76}"() #0
+ %sgpr77 = tail call i32 asm sideeffect "s_mov_b32 s77, 0", "={s77}"() #0
+ %sgpr78 = tail call i32 asm sideeffect "s_mov_b32 s78, 0", "={s78}"() #0
+ %sgpr79 = tail call i32 asm sideeffect "s_mov_b32 s79, 0", "={s79}"() #0
+ %sgpr80 = tail call i32 asm sideeffect "s_mov_b32 s80, 0", "={s80}"() #0
+ %sgpr81 = tail call i32 asm sideeffect "s_mov_b32 s81, 0", "={s81}"() #0
+ %sgpr82 = tail call i32 asm sideeffect "s_mov_b32 s82, 0", "={s82}"() #0
+ %sgpr83 = tail call i32 asm sideeffect "s_mov_b32 s83, 0", "={s83}"() #0
+ %sgpr84 = tail call i32 asm sideeffect "s_mov_b32 s84, 0", "={s84}"() #0
+ %sgpr85 = tail call i32 asm sideeffect "s_mov_b32 s85, 0", "={s85}"() #0
+ %sgpr86 = tail call i32 asm sideeffect "s_mov_b32 s86, 0", "={s86}"() #0
+ %sgpr87 = tail call i32 asm sideeffect "s_mov_b32 s87, 0", "={s87}"() #0
+ %sgpr88 = tail call i32 asm sideeffect "s_mov_b32 s88, 0", "={s88}"() #0
+ %sgpr89 = tail call i32 asm sideeffect "s_mov_b32 s89, 0", "={s89}"() #0
+ %sgpr90 = tail call i32 asm sideeffect "s_mov_b32 s90, 0", "={s90}"() #0
+ %sgpr91 = tail call i32 asm sideeffect "s_mov_b32 s91, 0", "={s91}"() #0
+ %sgpr92 = tail call i32 asm sideeffect "s_mov_b32 s92, 0", "={s92}"() #0
+ %sgpr93 = tail call i32 asm sideeffect "s_mov_b32 s93, 0", "={s93}"() #0
+ %sgpr94 = tail call i32 asm sideeffect "s_mov_b32 s94, 0", "={s94}"() #0
+ %sgpr95 = tail call i32 asm sideeffect "s_mov_b32 s95, 0", "={s95}"() #0
+ %sgpr96 = tail call i32 asm sideeffect "s_mov_b32 s96, 0", "={s96}"() #0
+ %sgpr97 = tail call i32 asm sideeffect "s_mov_b32 s97, 0", "={s97}"() #0
+ %sgpr98 = tail call i32 asm sideeffect "s_mov_b32 s98, 0", "={s98}"() #0
+ %sgpr99 = tail call i32 asm sideeffect "s_mov_b32 s99, 0", "={s99}"() #0
+ %sgpr100 = tail call i32 asm sideeffect "s_mov_b32 s100, 0", "={s100}"() #0
+ %sgpr101 = tail call i32 asm sideeffect "s_mov_b32 s101, 0", "={s101}"() #0
+ %sgpr102 = tail call i32 asm sideeffect "s_mov_b32 s102, 0", "={s102}"() #0
+ %sgpr103 = tail call i32 asm sideeffect "s_mov_b32 s103, 0", "={s103}"() #0
%vcc_lo = tail call i32 asm sideeffect "s_mov_b32 $0, 0", "={VCC_LO}"() #0
%vcc_hi = tail call i32 asm sideeffect "s_mov_b32 $0, 0", "={VCC_HI}"() #0
%cmp = icmp eq i32 %cnd, 0
@@ -126,112 +126,112 @@ bb2: ; 28 bytes
br label %bb3
bb3:
- tail call void asm sideeffect "; reg use $0", "{SGPR0}"(i32 %sgpr0) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR1}"(i32 %sgpr1) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR2}"(i32 %sgpr2) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR3}"(i32 %sgpr3) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR4}"(i32 %sgpr4) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR5}"(i32 %sgpr5) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR6}"(i32 %sgpr6) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR7}"(i32 %sgpr7) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR8}"(i32 %sgpr8) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR9}"(i32 %sgpr9) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR10}"(i32 %sgpr10) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR11}"(i32 %sgpr11) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR12}"(i32 %sgpr12) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR13}"(i32 %sgpr13) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR14}"(i32 %sgpr14) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR15}"(i32 %sgpr15) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR16}"(i32 %sgpr16) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR17}"(i32 %sgpr17) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR18}"(i32 %sgpr18) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR19}"(i32 %sgpr19) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR20}"(i32 %sgpr20) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR21}"(i32 %sgpr21) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR22}"(i32 %sgpr22) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR23}"(i32 %sgpr23) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR24}"(i32 %sgpr24) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR25}"(i32 %sgpr25) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR26}"(i32 %sgpr26) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR27}"(i32 %sgpr27) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR28}"(i32 %sgpr28) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR29}"(i32 %sgpr29) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR30}"(i32 %sgpr30) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR31}"(i32 %sgpr31) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR32}"(i32 %sgpr32) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR33}"(i32 %sgpr33) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR34}"(i32 %sgpr34) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR35}"(i32 %sgpr35) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR36}"(i32 %sgpr36) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR37}"(i32 %sgpr37) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR38}"(i32 %sgpr38) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR39}"(i32 %sgpr39) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR40}"(i32 %sgpr40) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR41}"(i32 %sgpr41) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR42}"(i32 %sgpr42) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR43}"(i32 %sgpr43) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR44}"(i32 %sgpr44) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR45}"(i32 %sgpr45) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR46}"(i32 %sgpr46) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR47}"(i32 %sgpr47) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR48}"(i32 %sgpr48) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR49}"(i32 %sgpr49) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR50}"(i32 %sgpr50) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR51}"(i32 %sgpr51) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR52}"(i32 %sgpr52) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR53}"(i32 %sgpr53) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR54}"(i32 %sgpr54) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR55}"(i32 %sgpr55) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR56}"(i32 %sgpr56) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR57}"(i32 %sgpr57) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR58}"(i32 %sgpr58) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR59}"(i32 %sgpr59) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR60}"(i32 %sgpr60) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR61}"(i32 %sgpr61) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR62}"(i32 %sgpr62) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR63}"(i32 %sgpr63) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR64}"(i32 %sgpr64) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR65}"(i32 %sgpr65) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR66}"(i32 %sgpr66) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR67}"(i32 %sgpr67) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR68}"(i32 %sgpr68) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR69}"(i32 %sgpr69) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR70}"(i32 %sgpr70) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR71}"(i32 %sgpr71) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR72}"(i32 %sgpr72) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR73}"(i32 %sgpr73) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR74}"(i32 %sgpr74) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR75}"(i32 %sgpr75) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR76}"(i32 %sgpr76) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR77}"(i32 %sgpr77) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR78}"(i32 %sgpr78) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR79}"(i32 %sgpr79) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR80}"(i32 %sgpr80) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR81}"(i32 %sgpr81) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR82}"(i32 %sgpr82) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR83}"(i32 %sgpr83) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR84}"(i32 %sgpr84) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR85}"(i32 %sgpr85) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR86}"(i32 %sgpr86) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR87}"(i32 %sgpr87) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR88}"(i32 %sgpr88) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR89}"(i32 %sgpr89) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR90}"(i32 %sgpr90) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR91}"(i32 %sgpr91) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR92}"(i32 %sgpr92) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR93}"(i32 %sgpr93) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR94}"(i32 %sgpr94) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR95}"(i32 %sgpr95) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR96}"(i32 %sgpr96) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR97}"(i32 %sgpr97) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR98}"(i32 %sgpr98) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR99}"(i32 %sgpr99) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR100}"(i32 %sgpr100) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR101}"(i32 %sgpr101) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR102}"(i32 %sgpr102) #0
- tail call void asm sideeffect "; reg use $0", "{SGPR103}"(i32 %sgpr103) #0
- tail call void asm sideeffect "; reg use $0", "{VCC_LO}"(i32 %vcc_lo) #0
- tail call void asm sideeffect "; reg use $0", "{VCC_HI}"(i32 %vcc_hi) #0
+ tail call void asm sideeffect "; reg use $0", "{s0}"(i32 %sgpr0) #0
+ tail call void asm sideeffect "; reg use $0", "{s1}"(i32 %sgpr1) #0
+ tail call void asm sideeffect "; reg use $0", "{s2}"(i32 %sgpr2) #0
+ tail call void asm sideeffect "; reg use $0", "{s3}"(i32 %sgpr3) #0
+ tail call void asm sideeffect "; reg use $0", "{s4}"(i32 %sgpr4) #0
+ tail call void asm sideeffect "; reg use $0", "{s5}"(i32 %sgpr5) #0
+ tail call void asm sideeffect "; reg use $0", "{s6}"(i32 %sgpr6) #0
+ tail call void asm sideeffect "; reg use $0", "{s7}"(i32 %sgpr7) #0
+ tail call void asm sideeffect "; reg use $0", "{s8}"(i32 %sgpr8) #0
+ tail call void asm sideeffect "; reg use $0", "{s9}"(i32 %sgpr9) #0
+ tail call void asm sideeffect "; reg use $0", "{s10}"(i32 %sgpr10) #0
+ tail call void asm sideeffect "; reg use $0", "{s11}"(i32 %sgpr11) #0
+ tail call void asm sideeffect "; reg use $0", "{s12}"(i32 %sgpr12) #0
+ tail call void asm sideeffect "; reg use $0", "{s13}"(i32 %sgpr13) #0
+ tail call void asm sideeffect "; reg use $0", "{s14}"(i32 %sgpr14) #0
+ tail call void asm sideeffect "; reg use $0", "{s15}"(i32 %sgpr15) #0
+ tail call void asm sideeffect "; reg use $0", "{s16}"(i32 %sgpr16) #0
+ tail call void asm sideeffect "; reg use $0", "{s17}"(i32 %sgpr17) #0
+ tail call void asm sideeffect "; reg use $0", "{s18}"(i32 %sgpr18) #0
+ tail call void asm sideeffect "; reg use $0", "{s19}"(i32 %sgpr19) #0
+ tail call void asm sideeffect "; reg use $0", "{s20}"(i32 %sgpr20) #0
+ tail call void asm sideeffect "; reg use $0", "{s21}"(i32 %sgpr21) #0
+ tail call void asm sideeffect "; reg use $0", "{s22}"(i32 %sgpr22) #0
+ tail call void asm sideeffect "; reg use $0", "{s23}"(i32 %sgpr23) #0
+ tail call void asm sideeffect "; reg use $0", "{s24}"(i32 %sgpr24) #0
+ tail call void asm sideeffect "; reg use $0", "{s25}"(i32 %sgpr25) #0
+ tail call void asm sideeffect "; reg use $0", "{s26}"(i32 %sgpr26) #0
+ tail call void asm sideeffect "; reg use $0", "{s27}"(i32 %sgpr27) #0
+ tail call void asm sideeffect "; reg use $0", "{s28}"(i32 %sgpr28) #0
+ tail call void asm sideeffect "; reg use $0", "{s29}"(i32 %sgpr29) #0
+ tail call void asm sideeffect "; reg use $0", "{s30}"(i32 %sgpr30) #0
+ tail call void asm sideeffect "; reg use $0", "{s31}"(i32 %sgpr31) #0
+ tail call void asm sideeffect "; reg use $0", "{s32}"(i32 %sgpr32) #0
+ tail call void asm sideeffect "; reg use $0", "{s33}"(i32 %sgpr33) #0
+ tail call void asm sideeffect "; reg use $0", "{s34}"(i32 %sgpr34) #0
+ tail call void asm sideeffect "; reg use $0", "{s35}"(i32 %sgpr35) #0
+ tail call void asm sideeffect "; reg use $0", "{s36}"(i32 %sgpr36) #0
+ tail call void asm sideeffect "; reg use $0", "{s37}"(i32 %sgpr37) #0
+ tail call void asm sideeffect "; reg use $0", "{s38}"(i32 %sgpr38) #0
+ tail call void asm sideeffect "; reg use $0", "{s39}"(i32 %sgpr39) #0
+ tail call void asm sideeffect "; reg use $0", "{s40}"(i32 %sgpr40) #0
+ tail call void asm sideeffect "; reg use $0", "{s41}"(i32 %sgpr41) #0
+ tail call void asm sideeffect "; reg use $0", "{s42}"(i32 %sgpr42) #0
+ tail call void asm sideeffect "; reg use $0", "{s43}"(i32 %sgpr43) #0
+ tail call void asm sideeffect "; reg use $0", "{s44}"(i32 %sgpr44) #0
+ tail call void asm sideeffect "; reg use $0", "{s45}"(i32 %sgpr45) #0
+ tail call void asm sideeffect "; reg use $0", "{s46}"(i32 %sgpr46) #0
+ tail call void asm sideeffect "; reg use $0", "{s47}"(i32 %sgpr47) #0
+ tail call void asm sideeffect "; reg use $0", "{s48}"(i32 %sgpr48) #0
+ tail call void asm sideeffect "; reg use $0", "{s49}"(i32 %sgpr49) #0
+ tail call void asm sideeffect "; reg use $0", "{s50}"(i32 %sgpr50) #0
+ tail call void asm sideeffect "; reg use $0", "{s51}"(i32 %sgpr51) #0
+ tail call void asm sideeffect "; reg use $0", "{s52}"(i32 %sgpr52) #0
+ tail call void asm sideeffect "; reg use $0", "{s53}"(i32 %sgpr53) #0
+ tail call void asm sideeffect "; reg use $0", "{s54}"(i32 %sgpr54) #0
+ tail call void asm sideeffect "; reg use $0", "{s55}"(i32 %sgpr55) #0
+ tail call void asm sideeffect "; reg use $0", "{s56}"(i32 %sgpr56) #0
+ tail call void asm sideeffect "; reg use $0", "{s57}"(i32 %sgpr57) #0
+ tail call void asm sideeffect "; reg use $0", "{s58}"(i32 %sgpr58) #0
+ tail call void asm sideeffect "; reg use $0", "{s59}"(i32 %sgpr59) #0
+ tail call void asm sideeffect "; reg use $0", "{s60}"(i32 %sgpr60) #0
+ tail call void asm sideeffect "; reg use $0", "{s61}"(i32 %sgpr61) #0
+ tail call void asm sideeffect "; reg use $0", "{s62}"(i32 %sgpr62) #0
+ tail call void asm sideeffect "; reg use $0", "{s63}"(i32 %sgpr63) #0
+ tail call void asm sideeffect "; reg use $0", "{s64}"(i32 %sgpr64) #0
+ tail call void asm sideeffect "; reg use $0", "{s65}"(i32 %sgpr65) #0
+ tail call void asm sideeffect "; reg use $0", "{s66}"(i32 %sgpr66) #0
+ tail call void asm sideeffect "; reg use $0", "{s67}"(i32 %sgpr67) #0
+ tail call void asm sideeffect "; reg use $0", "{s68}"(i32 %sgpr68) #0
+ tail call void asm sideeffect "; reg use $0", "{s69}"(i32 %sgpr69) #0
+ tail call void asm sideeffect "; reg use $0", "{s70}"(i32 %sgpr70) #0
+ tail call void asm sideeffect "; reg use $0", "{s71}"(i32 %sgpr71) #0
+ tail call void asm sideeffect "; reg use $0", "{s72}"(i32 %sgpr72) #0
+ tail call void asm sideeffect "; reg use $0", "{s73}"(i32 %sgpr73) #0
+ tail call void asm sideeffect "; reg use $0", "{s74}"(i32 %sgpr74) #0
+ tail call void asm sideeffect "; reg use $0", "{s75}"(i32 %sgpr75) #0
+ tail call void asm sideeffect "; reg use $0", "{s76}"(i32 %sgpr76) #0
+ tail call void asm sideeffect "; reg use $0", "{s77}"(i32 %sgpr77) #0
+ tail call void asm sideeffect "; reg use $0", "{s78}"(i32 %sgpr78) #0
+ tail call void asm sideeffect "; reg use $0", "{s79}"(i32 %sgpr79) #0
+ tail call void asm sideeffect "; reg use $0", "{s80}"(i32 %sgpr80) #0
+ tail call void asm sideeffect "; reg use $0", "{s81}"(i32 %sgpr81) #0
+ tail call void asm sideeffect "; reg use $0", "{s82}"(i32 %sgpr82) #0
+ tail call void asm sideeffect "; reg use $0", "{s83}"(i32 %sgpr83) #0
+ tail call void asm sideeffect "; reg use $0", "{s84}"(i32 %sgpr84) #0
+ tail call void asm sideeffect "; reg use $0", "{s85}"(i32 %sgpr85) #0
+ tail call void asm sideeffect "; reg use $0", "{s86}"(i32 %sgpr86) #0
+ tail call void asm sideeffect "; reg use $0", "{s87}"(i32 %sgpr87) #0
+ tail call void asm sideeffect "; reg use $0", "{s88}"(i32 %sgpr88) #0
+ tail call void asm sideeffect "; reg use $0", "{s89}"(i32 %sgpr89) #0
+ tail call void asm sideeffect "; reg use $0", "{s90}"(i32 %sgpr90) #0
+ tail call void asm sideeffect "; reg use $0", "{s91}"(i32 %sgpr91) #0
+ tail call void asm sideeffect "; reg use $0", "{s92}"(i32 %sgpr92) #0
+ tail call void asm sideeffect "; reg use $0", "{s93}"(i32 %sgpr93) #0
+ tail call void asm sideeffect "; reg use $0", "{s94}"(i32 %sgpr94) #0
+ tail call void asm sideeffect "; reg use $0", "{s95}"(i32 %sgpr95) #0
+ tail call void asm sideeffect "; reg use $0", "{s96}"(i32 %sgpr96) #0
+ tail call void asm sideeffect "; reg use $0", "{s97}"(i32 %sgpr97) #0
+ tail call void asm sideeffect "; reg use $0", "{s98}"(i32 %sgpr98) #0
+ tail call void asm sideeffect "; reg use $0", "{s99}"(i32 %sgpr99) #0
+ tail call void asm sideeffect "; reg use $0", "{s100}"(i32 %sgpr100) #0
+ tail call void asm sideeffect "; reg use $0", "{s101}"(i32 %sgpr101) #0
+ tail call void asm sideeffect "; reg use $0", "{s102}"(i32 %sgpr102) #0
+ tail call void asm sideeffect "; reg use $0", "{s103}"(i32 %sgpr103) #0
+ tail call void asm sideeffect "; reg use $0", "{vcc_lo}"(i32 %vcc_lo) #0
+ tail call void asm sideeffect "; reg use $0", "{vcc_hi}"(i32 %vcc_hi) #0
ret void
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/exceed-max-sgprs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/exceed-max-sgprs.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/exceed-max-sgprs.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/exceed-max-sgprs.ll Thu Jun 8 14:03:20 2017
@@ -2,97 +2,97 @@
; ERROR: error: scalar registers limit of 104 exceeded (106) in use_too_many_sgprs_tahiti
define amdgpu_kernel void @use_too_many_sgprs_tahiti() #0 {
- call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" ()
- call void asm sideeffect "", "~{SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15}" ()
- call void asm sideeffect "", "~{SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23}" ()
- call void asm sideeffect "", "~{SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31}" ()
- call void asm sideeffect "", "~{SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39}" ()
- call void asm sideeffect "", "~{SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47}" ()
- call void asm sideeffect "", "~{SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55}" ()
- call void asm sideeffect "", "~{SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63}" ()
- call void asm sideeffect "", "~{SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71}" ()
- call void asm sideeffect "", "~{SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79}" ()
- call void asm sideeffect "", "~{SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87}" ()
- call void asm sideeffect "", "~{SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95}" ()
- call void asm sideeffect "", "~{SGPR96_SGPR97_SGPR98_SGPR99_SGPR100_SGPR101_SGPR102_SGPR103}" ()
- call void asm sideeffect "", "~{VCC}" ()
+ call void asm sideeffect "", "~{s[0:7]}" ()
+ call void asm sideeffect "", "~{s[8:15]}" ()
+ call void asm sideeffect "", "~{s[16:23]}" ()
+ call void asm sideeffect "", "~{s[24:31]}" ()
+ call void asm sideeffect "", "~{s[32:39]}" ()
+ call void asm sideeffect "", "~{s[40:47]}" ()
+ call void asm sideeffect "", "~{s[48:55]}" ()
+ call void asm sideeffect "", "~{s[56:63]}" ()
+ call void asm sideeffect "", "~{s[64:71]}" ()
+ call void asm sideeffect "", "~{s[72:79]}" ()
+ call void asm sideeffect "", "~{s[80:87]}" ()
+ call void asm sideeffect "", "~{s[88:95]}" ()
+ call void asm sideeffect "", "~{s[96:103]}" ()
+ call void asm sideeffect "", "~{vcc}" ()
ret void
}
; ERROR: error: scalar registers limit of 104 exceeded (106) in use_too_many_sgprs_bonaire
define amdgpu_kernel void @use_too_many_sgprs_bonaire() #1 {
- call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" ()
- call void asm sideeffect "", "~{SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15}" ()
- call void asm sideeffect "", "~{SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23}" ()
- call void asm sideeffect "", "~{SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31}" ()
- call void asm sideeffect "", "~{SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39}" ()
- call void asm sideeffect "", "~{SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47}" ()
- call void asm sideeffect "", "~{SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55}" ()
- call void asm sideeffect "", "~{SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63}" ()
- call void asm sideeffect "", "~{SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71}" ()
- call void asm sideeffect "", "~{SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79}" ()
- call void asm sideeffect "", "~{SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87}" ()
- call void asm sideeffect "", "~{SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95}" ()
- call void asm sideeffect "", "~{SGPR96_SGPR97_SGPR98_SGPR99_SGPR100_SGPR101_SGPR102_SGPR103}" ()
- call void asm sideeffect "", "~{VCC}" ()
+ call void asm sideeffect "", "~{s[0:7]}" ()
+ call void asm sideeffect "", "~{s[8:15]}" ()
+ call void asm sideeffect "", "~{s[16:23]}" ()
+ call void asm sideeffect "", "~{s[24:31]}" ()
+ call void asm sideeffect "", "~{s[32:39]}" ()
+ call void asm sideeffect "", "~{s[40:47]}" ()
+ call void asm sideeffect "", "~{s[48:55]}" ()
+ call void asm sideeffect "", "~{s[56:63]}" ()
+ call void asm sideeffect "", "~{s[64:71]}" ()
+ call void asm sideeffect "", "~{s[72:79]}" ()
+ call void asm sideeffect "", "~{s[80:87]}" ()
+ call void asm sideeffect "", "~{s[88:95]}" ()
+ call void asm sideeffect "", "~{s[96:103]}" ()
+ call void asm sideeffect "", "~{vcc}" ()
ret void
}
; ERROR: error: scalar registers limit of 104 exceeded (108) in use_too_many_sgprs_bonaire_flat_scr
define amdgpu_kernel void @use_too_many_sgprs_bonaire_flat_scr() #1 {
- call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" ()
- call void asm sideeffect "", "~{SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15}" ()
- call void asm sideeffect "", "~{SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23}" ()
- call void asm sideeffect "", "~{SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31}" ()
- call void asm sideeffect "", "~{SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39}" ()
- call void asm sideeffect "", "~{SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47}" ()
- call void asm sideeffect "", "~{SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55}" ()
- call void asm sideeffect "", "~{SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63}" ()
- call void asm sideeffect "", "~{SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71}" ()
- call void asm sideeffect "", "~{SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79}" ()
- call void asm sideeffect "", "~{SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87}" ()
- call void asm sideeffect "", "~{SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95}" ()
- call void asm sideeffect "", "~{SGPR96_SGPR97_SGPR98_SGPR99_SGPR100_SGPR101_SGPR102_SGPR103}" ()
- call void asm sideeffect "", "~{VCC}" ()
- call void asm sideeffect "", "~{FLAT_SCR}" ()
+ call void asm sideeffect "", "~{s[0:7]}" ()
+ call void asm sideeffect "", "~{s[8:15]}" ()
+ call void asm sideeffect "", "~{s[16:23]}" ()
+ call void asm sideeffect "", "~{s[24:31]}" ()
+ call void asm sideeffect "", "~{s[32:39]}" ()
+ call void asm sideeffect "", "~{s[40:47]}" ()
+ call void asm sideeffect "", "~{s[48:55]}" ()
+ call void asm sideeffect "", "~{s[56:63]}" ()
+ call void asm sideeffect "", "~{s[64:71]}" ()
+ call void asm sideeffect "", "~{s[72:79]}" ()
+ call void asm sideeffect "", "~{s[80:87]}" ()
+ call void asm sideeffect "", "~{s[88:95]}" ()
+ call void asm sideeffect "", "~{s[96:103]}" ()
+ call void asm sideeffect "", "~{vcc}" ()
+ call void asm sideeffect "", "~{flat_scratch}" ()
ret void
}
; ERROR: error: scalar registers limit of 96 exceeded (98) in use_too_many_sgprs_iceland
define amdgpu_kernel void @use_too_many_sgprs_iceland() #2 {
- call void asm sideeffect "", "~{VCC}" ()
- call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" ()
- call void asm sideeffect "", "~{SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15}" ()
- call void asm sideeffect "", "~{SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23}" ()
- call void asm sideeffect "", "~{SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31}" ()
- call void asm sideeffect "", "~{SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39}" ()
- call void asm sideeffect "", "~{SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47}" ()
- call void asm sideeffect "", "~{SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55}" ()
- call void asm sideeffect "", "~{SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63}" ()
- call void asm sideeffect "", "~{SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71}" ()
- call void asm sideeffect "", "~{SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79}" ()
- call void asm sideeffect "", "~{SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87}" ()
- call void asm sideeffect "", "~{SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95}" ()
+ call void asm sideeffect "", "~{vcc}" ()
+ call void asm sideeffect "", "~{s[0:7]}" ()
+ call void asm sideeffect "", "~{s[8:15]}" ()
+ call void asm sideeffect "", "~{s[16:23]}" ()
+ call void asm sideeffect "", "~{s[24:31]}" ()
+ call void asm sideeffect "", "~{s[32:39]}" ()
+ call void asm sideeffect "", "~{s[40:47]}" ()
+ call void asm sideeffect "", "~{s[48:55]}" ()
+ call void asm sideeffect "", "~{s[56:63]}" ()
+ call void asm sideeffect "", "~{s[64:71]}" ()
+ call void asm sideeffect "", "~{s[72:79]}" ()
+ call void asm sideeffect "", "~{s[80:87]}" ()
+ call void asm sideeffect "", "~{s[88:95]}" ()
ret void
}
; ERROR: error: addressable scalar registers limit of 102 exceeded (103) in use_too_many_sgprs_fiji
define amdgpu_kernel void @use_too_many_sgprs_fiji() #3 {
- call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" ()
- call void asm sideeffect "", "~{SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15}" ()
- call void asm sideeffect "", "~{SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23}" ()
- call void asm sideeffect "", "~{SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31}" ()
- call void asm sideeffect "", "~{SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39}" ()
- call void asm sideeffect "", "~{SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47}" ()
- call void asm sideeffect "", "~{SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55}" ()
- call void asm sideeffect "", "~{SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63}" ()
- call void asm sideeffect "", "~{SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71}" ()
- call void asm sideeffect "", "~{SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79}" ()
- call void asm sideeffect "", "~{SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87}" ()
- call void asm sideeffect "", "~{SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95}" ()
- call void asm sideeffect "", "~{SGPR96_SGPR97_SGPR98_SGPR99}" ()
- call void asm sideeffect "", "~{SGPR100_SGPR101}" ()
- call void asm sideeffect "", "~{SGPR102}" ()
+ call void asm sideeffect "", "~{s[0:7]}" ()
+ call void asm sideeffect "", "~{s[8:15]}" ()
+ call void asm sideeffect "", "~{s[16:23]}" ()
+ call void asm sideeffect "", "~{s[24:31]}" ()
+ call void asm sideeffect "", "~{s[32:39]}" ()
+ call void asm sideeffect "", "~{s[40:47]}" ()
+ call void asm sideeffect "", "~{s[48:55]}" ()
+ call void asm sideeffect "", "~{s[56:63]}" ()
+ call void asm sideeffect "", "~{s[64:71]}" ()
+ call void asm sideeffect "", "~{s[72:79]}" ()
+ call void asm sideeffect "", "~{s[80:87]}" ()
+ call void asm sideeffect "", "~{s[88:95]}" ()
+ call void asm sideeffect "", "~{s[96:99]}" ()
+ call void asm sideeffect "", "~{s[100:101]}" ()
+ call void asm sideeffect "", "~{s102}" ()
ret void
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/flat-scratch-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/flat-scratch-reg.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/flat-scratch-reg.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/flat-scratch-reg.ll Thu Jun 8 14:03:20 2017
@@ -21,7 +21,7 @@
; VI-XNACK: ; NumSgprs: 12
define amdgpu_kernel void @no_vcc_no_flat() {
entry:
- call void asm sideeffect "", "~{SGPR7}"()
+ call void asm sideeffect "", "~{s7}"()
ret void
}
@@ -35,7 +35,7 @@ entry:
; VI-XNACK: ; NumSgprs: 12
define amdgpu_kernel void @vcc_no_flat() {
entry:
- call void asm sideeffect "", "~{SGPR7},~{VCC}"()
+ call void asm sideeffect "", "~{s7},~{vcc}"()
ret void
}
@@ -52,7 +52,7 @@ entry:
; HSA-VI-XNACK: ; NumSgprs: 14
define amdgpu_kernel void @no_vcc_flat() {
entry:
- call void asm sideeffect "", "~{SGPR7},~{FLAT_SCR}"()
+ call void asm sideeffect "", "~{s7},~{flat_scratch}"()
ret void
}
@@ -68,7 +68,7 @@ entry:
; HSA-VI-XNACK: ; NumSgprs: 14
define amdgpu_kernel void @vcc_flat() {
entry:
- call void asm sideeffect "", "~{SGPR7},~{VCC},~{FLAT_SCR}"()
+ call void asm sideeffect "", "~{s7},~{vcc},~{flat_scratch}"()
ret void
}
@@ -81,7 +81,7 @@ entry:
; VI-XNACK: NumSgprs: 6
define amdgpu_kernel void @use_flat_scr() #0 {
entry:
- call void asm sideeffect "; clobber ", "~{FLAT_SCR}"()
+ call void asm sideeffect "; clobber ", "~{flat_scratch}"()
ret void
}
@@ -91,7 +91,7 @@ entry:
; VI-XNACK: NumSgprs: 6
define amdgpu_kernel void @use_flat_scr_lo() #0 {
entry:
- call void asm sideeffect "; clobber ", "~{FLAT_SCR_LO}"()
+ call void asm sideeffect "; clobber ", "~{flat_scratch_lo}"()
ret void
}
@@ -101,7 +101,7 @@ entry:
; VI-XNACK: NumSgprs: 6
define amdgpu_kernel void @use_flat_scr_hi() #0 {
entry:
- call void asm sideeffect "; clobber ", "~{FLAT_SCR_HI}"()
+ call void asm sideeffect "; clobber ", "~{flat_scratch_hi}"()
ret void
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll Thu Jun 8 14:03:20 2017
@@ -5,40 +5,40 @@
; GCN: ; illegal copy v1 to s9
define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_i32() #0 {
- %vgpr = call i32 asm sideeffect "; def $0", "=${VGPR1}"()
- call void asm sideeffect "; use $0", "${SGPR9}"(i32 %vgpr)
+ %vgpr = call i32 asm sideeffect "; def $0", "=${v1}"()
+ call void asm sideeffect "; use $0", "${s9}"(i32 %vgpr)
ret void
}
; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v2i32 void (): illegal SGPR to VGPR copy
; GCN: ; illegal copy v[0:1] to s[10:11]
define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_v2i32() #0 {
- %vgpr = call <2 x i32> asm sideeffect "; def $0", "=${VGPR0_VGPR1}"()
- call void asm sideeffect "; use $0", "${SGPR10_SGPR11}"(<2 x i32> %vgpr)
+ %vgpr = call <2 x i32> asm sideeffect "; def $0", "=${v[0:1]}"()
+ call void asm sideeffect "; use $0", "${s[10:11]}"(<2 x i32> %vgpr)
ret void
}
; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v4i32 void (): illegal SGPR to VGPR copy
; GCN: ; illegal copy v[0:3] to s[8:11]
define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_v4i32() #0 {
- %vgpr = call <4 x i32> asm sideeffect "; def $0", "=${VGPR0_VGPR1_VGPR2_VGPR3}"()
- call void asm sideeffect "; use $0", "${SGPR8_SGPR9_SGPR10_SGPR11}"(<4 x i32> %vgpr)
+ %vgpr = call <4 x i32> asm sideeffect "; def $0", "=${v[0:3]}"()
+ call void asm sideeffect "; use $0", "${s[8:11]}"(<4 x i32> %vgpr)
ret void
}
; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v8i32 void (): illegal SGPR to VGPR copy
; GCN: ; illegal copy v[0:7] to s[8:15]
define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_v8i32() #0 {
- %vgpr = call <8 x i32> asm sideeffect "; def $0", "=${VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7}"()
- call void asm sideeffect "; use $0", "${SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15}"(<8 x i32> %vgpr)
+ %vgpr = call <8 x i32> asm sideeffect "; def $0", "=${v[0:7]}"()
+ call void asm sideeffect "; use $0", "${s[8:15]}"(<8 x i32> %vgpr)
ret void
}
; ERR error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v16i32 void (): illegal SGPR to VGPR copy
; GCN: ; illegal copy v[0:15] to s[16:31]
define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_v16i32() #0 {
- %vgpr = call <16 x i32> asm sideeffect "; def $0", "=${VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15}"()
- call void asm sideeffect "; use $0", "${SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31}"(<16 x i32> %vgpr)
+ %vgpr = call <16 x i32> asm sideeffect "; def $0", "=${v[0:15]}"()
+ call void asm sideeffect "; use $0", "${s[16:31]}"(<16 x i32> %vgpr)
ret void
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll Thu Jun 8 14:03:20 2017
@@ -379,7 +379,7 @@ entry:
%idx0 = load volatile i32, i32 addrspace(1)* %gep
%idx1 = add i32 %idx0, 1
%val0 = extractelement <4 x i32> <i32 7, i32 9, i32 11, i32 13>, i32 %idx0
- %live.out.reg = call i32 asm sideeffect "s_mov_b32 $0, 17", "={SGPR4}" ()
+ %live.out.reg = call i32 asm sideeffect "s_mov_b32 $0, 17", "={s4}" ()
%val1 = extractelement <4 x i32> <i32 7, i32 9, i32 11, i32 13>, i32 %idx1
store volatile i32 %val0, i32 addrspace(1)* %out0
store volatile i32 %val1, i32 addrspace(1)* %out0
Modified: llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll Thu Jun 8 14:03:20 2017
@@ -193,7 +193,7 @@ entry:
; CHECK: use v[0:1]
define amdgpu_kernel void @i64_imm_input_phys_vgpr() {
entry:
- call void asm sideeffect "; use $0 ", "{VGPR0_VGPR1}"(i64 123456)
+ call void asm sideeffect "; use $0 ", "{v[0:1]}"(i64 123456)
ret void
}
@@ -202,7 +202,7 @@ entry:
; CHECK: ; use v0
define amdgpu_kernel void @i1_imm_input_phys_vgpr() {
entry:
- call void asm sideeffect "; use $0 ", "{VGPR0}"(i1 true)
+ call void asm sideeffect "; use $0 ", "{v0}"(i1 true)
ret void
}
@@ -215,7 +215,7 @@ entry:
define amdgpu_kernel void @i1_input_phys_vgpr() {
entry:
%val = load i1, i1 addrspace(1)* undef
- call void asm sideeffect "; use $0 ", "{VGPR0}"(i1 %val)
+ call void asm sideeffect "; use $0 ", "{v0}"(i1 %val)
ret void
}
@@ -229,7 +229,7 @@ define amdgpu_kernel void @i1_input_phys
entry:
%val0 = load volatile i1, i1 addrspace(1)* undef
%val1 = load volatile i1, i1 addrspace(1)* undef
- call void asm sideeffect "; use $0 $1 ", "{VGPR0}, {VGPR1}"(i1 %val0, i1 %val1)
+ call void asm sideeffect "; use $0 $1 ", "{v0}, {v1}"(i1 %val0, i1 %val1)
ret void
}
@@ -240,8 +240,8 @@ entry:
; CHECK: v_lshlrev_b32_e32 v{{[0-9]+}}, v0, v1
define amdgpu_kernel void @muliple_def_phys_vgpr() {
entry:
- %def0 = call i32 asm sideeffect "; def $0 ", "={VGPR0}"()
- %def1 = call i32 asm sideeffect "; def $0 ", "={VGPR0}"()
+ %def0 = call i32 asm sideeffect "; def $0 ", "={v0}"()
+ %def1 = call i32 asm sideeffect "; def $0 ", "={v0}"()
%add = shl i32 %def0, %def1
store i32 %add, i32 addrspace(1)* undef
ret void
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll Thu Jun 8 14:03:20 2017
@@ -8,9 +8,9 @@ declare i64 @llvm.amdgcn.mqsad.pk.u16.u8
; GCN-DAG: v_mov_b32_e32 v5, v1
; GCN-DAG: v_mov_b32_e32 v4, v0
define amdgpu_kernel void @v_mqsad_pk_u16_u8(i64 addrspace(1)* %out, i64 %src) {
- %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={VGPR4_VGPR5},v"(i64 %src) #0
+ %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[4:5]},v"(i64 %src) #0
%tmp1 = call i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64 %tmp, i32 100, i64 100) #0
- %tmp2 = call i64 asm ";; force constraint", "=v,{VGPR4_VGPR5}"(i64 %tmp1) #0
+ %tmp2 = call i64 asm ";; force constraint", "=v,{v[4:5]}"(i64 %tmp1) #0
store i64 %tmp2, i64 addrspace(1)* %out, align 4
ret void
}
@@ -18,15 +18,15 @@ define amdgpu_kernel void @v_mqsad_pk_u1
; GCN-LABEL: {{^}}v_mqsad_pk_u16_u8_non_immediate:
; GCN: v_mqsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
; GCN-DAG: v_mov_b32_e32 v3, v1
-; GCN-DAG: v_mov_b32_e32 v2, v0
+; GCN-DAG: v_mov_b32_e32 v2, v0
define amdgpu_kernel void @v_mqsad_pk_u16_u8_non_immediate(i64 addrspace(1)* %out, i64 %src, i32 %a, i64 %b) {
- %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={VGPR2_VGPR3},v"(i64 %src) #0
- %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={VGPR4},v"(i32 %a) #0
- %tmp2 = call i64 asm "v_lshlrev_b64 $0, $1, 1", "={VGPR6_VGPR7},v"(i64 %b) #0
+ %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
+ %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
+ %tmp2 = call i64 asm "v_lshlrev_b64 $0, $1, 1", "={v[6:7]},v"(i64 %b) #0
%tmp3 = call i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64 %tmp, i32 %tmp1, i64 %tmp2) #0
- %tmp4 = call i64 asm ";; force constraint", "=v,{VGPR2_VGPR3}"(i64 %tmp3) #0
+ %tmp4 = call i64 asm ";; force constraint", "=v,{v[2:3]}"(i64 %tmp3) #0
store i64 %tmp4, i64 addrspace(1)* %out, align 4
ret void
}
-attributes #0 = { nounwind readnone }
\ No newline at end of file
+attributes #0 = { nounwind readnone }
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll Thu Jun 8 14:03:20 2017
@@ -5,55 +5,55 @@ declare <4 x i32> @llvm.amdgcn.mqsad.u32
; GCN-LABEL: {{^}}v_mqsad_u32_u8_inline_integer_immediate:
; GCN-DAG: v_mov_b32_e32 v0, v2
-; GCN-DAG: v_mov_b32_e32 v1, v3
+; GCN-DAG: v_mov_b32_e32 v1, v3
; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @v_mqsad_u32_u8_inline_integer_immediate(<4 x i32> addrspace(1)* %out, i64 %src, i32 %a) {
- %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={VGPR2_VGPR3},v"(i64 %src) #0
- %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={VGPR4},v"(i32 %a) #0
+ %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
+ %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
%tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> <i32 10, i32 20, i32 30, i32 40>) #0
- %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{VGPR2_VGPR3_VGPR4_VGPR5}"(<4 x i32> %tmp2) #0
+ %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #0
store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 4
ret void
}
; GCN-LABEL: {{^}}v_mqsad_u32_u8_non_immediate:
; GCN-DAG: v_mov_b32_e32 v0, v2
-; GCN-DAG: v_mov_b32_e32 v1, v3
+; GCN-DAG: v_mov_b32_e32 v1, v3
; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @v_mqsad_u32_u8_non_immediate(<4 x i32> addrspace(1)* %out, i64 %src, i32 %a, <4 x i32> %b) {
- %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={VGPR2_VGPR3},v"(i64 %src) #0
- %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={VGPR4},v"(i32 %a) #0
+ %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
+ %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
%tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> %b) #0
- %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{VGPR2_VGPR3_VGPR4_VGPR5}"(<4 x i32> %tmp2) #0
+ %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #0
store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 4
ret void
}
; GCN-LABEL: {{^}}v_mqsad_u32_u8_inline_fp_immediate:
; GCN-DAG: v_mov_b32_e32 v0, v2
-; GCN-DAG: v_mov_b32_e32 v1, v3
+; GCN-DAG: v_mov_b32_e32 v1, v3
; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @v_mqsad_u32_u8_inline_fp_immediate(<4 x i32> addrspace(1)* %out, i64 %src, i32 %a) {
- %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={VGPR2_VGPR3},v"(i64 %src) #0
- %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={VGPR4},v"(i32 %a) #0
+ %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
+ %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
%tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> <i32 1065353216, i32 0, i32 0, i32 0>) #0
- %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{VGPR2_VGPR3_VGPR4_VGPR5}"(<4 x i32> %tmp2) #0
+ %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #0
store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 4
ret void
}
; GCN-LABEL: {{^}}v_mqsad_u32_u8_use_sgpr_vgpr:
; GCN-DAG: v_mov_b32_e32 v0, v2
-; GCN-DAG: v_mov_b32_e32 v1, v3
+; GCN-DAG: v_mov_b32_e32 v1, v3
; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @v_mqsad_u32_u8_use_sgpr_vgpr(<4 x i32> addrspace(1)* %out, i64 %src, i32 %a, <4 x i32> addrspace(1)* %input) {
%in = load <4 x i32>, <4 x i32> addrspace(1) * %input
- %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={VGPR2_VGPR3},v"(i64 %src) #0
- %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={VGPR4},v"(i32 %a) #0
+ %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
+ %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
%tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> %in) #0
- %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{VGPR2_VGPR3_VGPR4_VGPR5}"(<4 x i32> %tmp2) #0
+ %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #0
store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 4
ret void
}
-attributes #0 = { nounwind readnone }
\ No newline at end of file
+attributes #0 = { nounwind readnone }
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll Thu Jun 8 14:03:20 2017
@@ -8,9 +8,9 @@ declare i64 @llvm.amdgcn.qsad.pk.u16.u8(
; GCN-DAG: v_mov_b32_e32 v5, v1
; GCN-DAG: v_mov_b32_e32 v4, v0
define amdgpu_kernel void @v_qsad_pk_u16_u8(i64 addrspace(1)* %out, i64 %src) {
- %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={VGPR4_VGPR5},v"(i64 %src) #0
+ %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[4:5]},v"(i64 %src) #0
%tmp1 = call i64 @llvm.amdgcn.qsad.pk.u16.u8(i64 %tmp, i32 100, i64 100) #0
- %tmp2 = call i64 asm ";; force constraint", "=v,{VGPR4_VGPR5}"(i64 %tmp1) #0
+ %tmp2 = call i64 asm ";; force constraint", "=v,{v[4:5]}"(i64 %tmp1) #0
store i64 %tmp2, i64 addrspace(1)* %out, align 4
ret void
}
@@ -20,11 +20,11 @@ define amdgpu_kernel void @v_qsad_pk_u16
; GCN-DAG: v_mov_b32_e32 v3, v1
; GCN-DAG: v_mov_b32_e32 v2, v0
define amdgpu_kernel void @v_qsad_pk_u16_u8_non_immediate(i64 addrspace(1)* %out, i64 %src, i32 %a, i64 %b) {
- %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={VGPR2_VGPR3},v"(i64 %src) #0
- %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={VGPR4},v"(i32 %a) #0
- %tmp2 = call i64 asm "v_lshlrev_b64 $0, $1, 1", "={VGPR6_VGPR7},v"(i64 %b) #0
+ %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
+ %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
+ %tmp2 = call i64 asm "v_lshlrev_b64 $0, $1, 1", "={v[6:7]},v"(i64 %b) #0
%tmp3 = call i64 @llvm.amdgcn.qsad.pk.u16.u8(i64 %tmp, i32 %tmp1, i64 %tmp2) #0
- %tmp4 = call i64 asm ";; force constraint", "=v,{VGPR2_VGPR3}"(i64 %tmp3) #0
+ %tmp4 = call i64 asm ";; force constraint", "=v,{v[2:3]}"(i64 %tmp3) #0
store i64 %tmp4, i64 addrspace(1)* %out, align 4
ret void
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll Thu Jun 8 14:03:20 2017
@@ -608,11 +608,11 @@ ret:
; GCN: ;;#ASMSTART
; GCN: ; use s[0:1]
define amdgpu_kernel void @no_vgprs_last_sgpr_spill(i32 addrspace(1)* %out, i32 %in) #1 {
- call void asm sideeffect "", "~{VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7}" () #0
- call void asm sideeffect "", "~{VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15}" () #0
- call void asm sideeffect "", "~{VGPR16_VGPR17_VGPR18_VGPR19}"() #0
- call void asm sideeffect "", "~{VGPR20_VGPR21}"() #0
- call void asm sideeffect "", "~{VGPR22}"() #0
+ call void asm sideeffect "", "~{v[0:7]}" () #0
+ call void asm sideeffect "", "~{v[8:15]}" () #0
+ call void asm sideeffect "", "~{v[16:19]}"() #0
+ call void asm sideeffect "", "~{v[20:21]}"() #0
+ call void asm sideeffect "", "~{v22}"() #0
%wide.sgpr0 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr1 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
Modified: llvm/trunk/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll Thu Jun 8 14:03:20 2017
@@ -25,50 +25,50 @@
; SMEM: s_dcache_wb
; ALL: s_endpgm
define amdgpu_kernel void @test(i32 addrspace(1)* %out, i32 %in) {
- call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" ()
- call void asm sideeffect "", "~{SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15}" ()
- call void asm sideeffect "", "~{SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23}" ()
- call void asm sideeffect "", "~{SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31}" ()
- call void asm sideeffect "", "~{SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39}" ()
- call void asm sideeffect "", "~{SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47}" ()
- call void asm sideeffect "", "~{SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55}" ()
- call void asm sideeffect "", "~{SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63}" ()
- call void asm sideeffect "", "~{SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71}" ()
- call void asm sideeffect "", "~{SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79}" ()
- call void asm sideeffect "", "~{SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87}" ()
- call void asm sideeffect "", "~{SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95}" ()
- call void asm sideeffect "", "~{VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7}" ()
- call void asm sideeffect "", "~{VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15}" ()
- call void asm sideeffect "", "~{VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23}" ()
- call void asm sideeffect "", "~{VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31}" ()
- call void asm sideeffect "", "~{VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39}" ()
- call void asm sideeffect "", "~{VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47}" ()
- call void asm sideeffect "", "~{VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55}" ()
- call void asm sideeffect "", "~{VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63}" ()
- call void asm sideeffect "", "~{VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71}" ()
- call void asm sideeffect "", "~{VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79}" ()
- call void asm sideeffect "", "~{VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87}" ()
- call void asm sideeffect "", "~{VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95}" ()
- call void asm sideeffect "", "~{VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103}" ()
- call void asm sideeffect "", "~{VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111}" ()
- call void asm sideeffect "", "~{VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119}" ()
- call void asm sideeffect "", "~{VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127}" ()
- call void asm sideeffect "", "~{VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135}" ()
- call void asm sideeffect "", "~{VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143}" ()
- call void asm sideeffect "", "~{VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151}" ()
- call void asm sideeffect "", "~{VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159}" ()
- call void asm sideeffect "", "~{VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167}" ()
- call void asm sideeffect "", "~{VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175}" ()
- call void asm sideeffect "", "~{VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183}" ()
- call void asm sideeffect "", "~{VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191}" ()
- call void asm sideeffect "", "~{VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199}" ()
- call void asm sideeffect "", "~{VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207}" ()
- call void asm sideeffect "", "~{VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215}" ()
- call void asm sideeffect "", "~{VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223}" ()
- call void asm sideeffect "", "~{VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231}" ()
- call void asm sideeffect "", "~{VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239}" ()
- call void asm sideeffect "", "~{VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247}" ()
- call void asm sideeffect "", "~{VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255}" ()
+ call void asm sideeffect "", "~{s[0:7]}" ()
+ call void asm sideeffect "", "~{s[8:15]}" ()
+ call void asm sideeffect "", "~{s[16:23]}" ()
+ call void asm sideeffect "", "~{s[24:31]}" ()
+ call void asm sideeffect "", "~{s[32:39]}" ()
+ call void asm sideeffect "", "~{s[40:47]}" ()
+ call void asm sideeffect "", "~{s[48:55]}" ()
+ call void asm sideeffect "", "~{s[56:63]}" ()
+ call void asm sideeffect "", "~{s[64:71]}" ()
+ call void asm sideeffect "", "~{s[72:79]}" ()
+ call void asm sideeffect "", "~{s[80:87]}" ()
+ call void asm sideeffect "", "~{s[88:95]}" ()
+ call void asm sideeffect "", "~{v[0:7]}" ()
+ call void asm sideeffect "", "~{v[8:15]}" ()
+ call void asm sideeffect "", "~{v[16:23]}" ()
+ call void asm sideeffect "", "~{v[24:31]}" ()
+ call void asm sideeffect "", "~{v[32:39]}" ()
+ call void asm sideeffect "", "~{v[40:47]}" ()
+ call void asm sideeffect "", "~{v[48:55]}" ()
+ call void asm sideeffect "", "~{v[56:63]}" ()
+ call void asm sideeffect "", "~{v[64:71]}" ()
+ call void asm sideeffect "", "~{v[72:79]}" ()
+ call void asm sideeffect "", "~{v[80:87]}" ()
+ call void asm sideeffect "", "~{v[88:95]}" ()
+ call void asm sideeffect "", "~{v[96:103]}" ()
+ call void asm sideeffect "", "~{v[104:111]}" ()
+ call void asm sideeffect "", "~{v[112:119]}" ()
+ call void asm sideeffect "", "~{v[120:127]}" ()
+ call void asm sideeffect "", "~{v[128:135]}" ()
+ call void asm sideeffect "", "~{v[136:143]}" ()
+ call void asm sideeffect "", "~{v[144:151]}" ()
+ call void asm sideeffect "", "~{v[152:159]}" ()
+ call void asm sideeffect "", "~{v[160:167]}" ()
+ call void asm sideeffect "", "~{v[168:175]}" ()
+ call void asm sideeffect "", "~{v[176:183]}" ()
+ call void asm sideeffect "", "~{v[184:191]}" ()
+ call void asm sideeffect "", "~{v[192:199]}" ()
+ call void asm sideeffect "", "~{v[200:207]}" ()
+ call void asm sideeffect "", "~{v[208:215]}" ()
+ call void asm sideeffect "", "~{v[216:223]}" ()
+ call void asm sideeffect "", "~{v[224:231]}" ()
+ call void asm sideeffect "", "~{v[232:239]}" ()
+ call void asm sideeffect "", "~{v[240:247]}" ()
+ call void asm sideeffect "", "~{v[248:255]}" ()
store i32 %in, i32 addrspace(1)* %out
ret void
Modified: llvm/trunk/test/CodeGen/AMDGPU/skip-if-dead.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/skip-if-dead.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/skip-if-dead.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/skip-if-dead.ll Thu Jun 8 14:03:20 2017
@@ -79,7 +79,7 @@ define amdgpu_ps void @test_kill_depth_v
; CHECK-NEXT: s_endpgm
define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 {
call void @llvm.AMDGPU.kill(float %x)
- %y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={VGPR7}"()
+ %y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={v7}"()
call void @llvm.AMDGPU.kill(float %y)
ret void
}
@@ -128,7 +128,7 @@ bb:
v_nop_e64
v_nop_e64
v_nop_e64
- v_nop_e64", "={VGPR7}"()
+ v_nop_e64", "={v7}"()
call void @llvm.AMDGPU.kill(float %var)
br label %exit
@@ -186,11 +186,11 @@ bb:
v_nop_e64
v_nop_e64
v_nop_e64
- v_nop_e64", "={VGPR7}"()
- %live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={VGPR8}"()
+ v_nop_e64", "={v7}"()
+ %live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={v8}"()
call void @llvm.AMDGPU.kill(float %var)
store volatile float %live.across, float addrspace(1)* undef
- %live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={VGPR9}"()
+ %live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={v9}"()
br label %exit
exit:
@@ -242,7 +242,7 @@ bb:
v_nop_e64
v_nop_e64
v_nop_e64
- v_nop_e64", "={VGPR7}"()
+ v_nop_e64", "={v7}"()
call void @llvm.AMDGPU.kill(float %var)
%vgpr = load volatile i32, i32 addrspace(1)* undef
%loop.cond = icmp eq i32 %vgpr, 0
Modified: llvm/trunk/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-scavenge-offset.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/spill-scavenge-offset.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/spill-scavenge-offset.ll Thu Jun 8 14:03:20 2017
@@ -20,13 +20,13 @@ entry:
%a = load <1280 x i32>, <1280 x i32> addrspace(1)* %aptr
; mark most VGPR registers as used to increase register pressure
- call void asm sideeffect "", "~{VGPR4},~{VGPR8},~{VGPR12},~{VGPR16},~{VGPR20},~{VGPR24},~{VGPR28},~{VGPR32}" ()
- call void asm sideeffect "", "~{VGPR36},~{VGPR40},~{VGPR44},~{VGPR48},~{VGPR52},~{VGPR56},~{VGPR60},~{VGPR64}" ()
- call void asm sideeffect "", "~{VGPR68},~{VGPR72},~{VGPR76},~{VGPR80},~{VGPR84},~{VGPR88},~{VGPR92},~{VGPR96}" ()
- call void asm sideeffect "", "~{VGPR100},~{VGPR104},~{VGPR108},~{VGPR112},~{VGPR116},~{VGPR120},~{VGPR124},~{VGPR128}" ()
- call void asm sideeffect "", "~{VGPR132},~{VGPR136},~{VGPR140},~{VGPR144},~{VGPR148},~{VGPR152},~{VGPR156},~{VGPR160}" ()
- call void asm sideeffect "", "~{VGPR164},~{VGPR168},~{VGPR172},~{VGPR176},~{VGPR180},~{VGPR184},~{VGPR188},~{VGPR192}" ()
- call void asm sideeffect "", "~{VGPR196},~{VGPR200},~{VGPR204},~{VGPR208},~{VGPR212},~{VGPR216},~{VGPR220},~{VGPR224}" ()
+ call void asm sideeffect "", "~{v4},~{v8},~{v12},~{v16},~{v20},~{v24},~{v28},~{v32}" ()
+ call void asm sideeffect "", "~{v36},~{v40},~{v44},~{v48},~{v52},~{v56},~{v60},~{v64}" ()
+ call void asm sideeffect "", "~{v68},~{v72},~{v76},~{v80},~{v84},~{v88},~{v92},~{v96}" ()
+ call void asm sideeffect "", "~{v100},~{v104},~{v108},~{v112},~{v116},~{v120},~{v124},~{v128}" ()
+ call void asm sideeffect "", "~{v132},~{v136},~{v140},~{v144},~{v148},~{v152},~{v156},~{v160}" ()
+ call void asm sideeffect "", "~{v164},~{v168},~{v172},~{v176},~{v180},~{v184},~{v188},~{v192}" ()
+ call void asm sideeffect "", "~{v196},~{v200},~{v204},~{v208},~{v212},~{v216},~{v220},~{v224}" ()
%outptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %out, i32 %tid
store <1280 x i32> %a, <1280 x i32> addrspace(1)* %outptr
Modified: llvm/trunk/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll?rev=305004&r1=305003&r2=305004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll Thu Jun 8 14:03:20 2017
@@ -73,14 +73,14 @@ bb11:
; CHECK: buffer_store_dwordx4 v{{\[}}[[OUTPUT_LO]]:[[OUTPUT_HI]]{{\]}}
define amdgpu_kernel void @partially_undef_copy() #0 {
- %tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={VGPR5}"()
- %tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={VGPR6}"()
+ %tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={v5}"()
+ %tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={v6}"()
%partially.undef.0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
%partially.undef.1 = insertelement <4 x i32> %partially.undef.0, i32 %tmp1, i32 0
store volatile <4 x i32> %partially.undef.1, <4 x i32> addrspace(1)* undef, align 16
- tail call void asm sideeffect "v_nop", "v={VGPR5_VGPR6_VGPR7_VGPR8}"(<4 x i32> %partially.undef.0)
+ tail call void asm sideeffect "v_nop", "v={v[5:8]}"(<4 x i32> %partially.undef.0)
ret void
}
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