[PATCH] D33690: [PowerPC] Match vec_revb builtins to P9 instructions.

[Tony Jiang via Phabricator via llvm-commits]

jtony added inline comments.


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Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:7909
+      return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveQWord);
+    }
+  }
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kbarton wrote:
> I'm probably missing something basic here, but why are we always converting the return to v16i8?
Base on my understanding, after legalization, the only legal vector type for vector_shuffle is v16i8, and also the return value for vector_shuffle is v16i8, if we want to replace vector_shuffle with PPCISD::XXREVERSE node, we want to keep the original return type. Otherwise, it will cause "LLVM ERROR: Cannot select" error.


If you look at the debug info, it is more clear. If I remove the bitcast to v16i8, for XXBRQ, we would do the following (note we changed the return type after DAG combine):



Legalizing: t5: v16i8 = vector_shuffle<15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0> t3, undef:v16i8
 ... replacing: t5: **v16i8 **= vector_shuffle<15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0> t3, undef:v16i8 with:     t11: **v1i128 **= PPCISD::XXREVERSE t2




This will eventually cause:
LLVM ERROR: **Cannot select: t6**: v1i128 = bitcast t11
  t11: v1i128 = PPCISD::XXREVERSE t2
    t2: v1i128,ch = CopyFromReg t0, Register:v1i128 %vreg0
      t1: v1i128 = Register %vreg0
In function: testXXBRQ

Therefore, we always need to cast the return value to v16i8. Correct me, if there is any improper understanding.




https://reviews.llvm.org/D33690