[PATCH] D33836: [AArch64] Enable FeatureFuseAES for the generic processor model.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

I had another look and it turns out I can’t add a microbenchmark for legal reasons. Unfortunately the only thing I can say is that back-to-back scheduling brings double digit performance improvements for code making heavy use of AES instructions on Cortex-A CPUs and refer to the public software optimization guides for Cortex-A72 and Cortex-A57, which both encourage this optimization.


https://reviews.llvm.org/D33836