[PATCH] D33728: [X86][SSE] Improve handling of non-temporal aligned loads

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:32303
   // For chips with slow 32-byte unaligned loads, break the 32-byte operation
-  // into two 16-byte operations.
+  // into two 16-byte operations. Also split non-temporal aligned loads on AVX1
+  // targets as 32-byte loads will lower to regular temporal loads.
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filcab wrote:
> "pre-AVX2" (or "targets without AVX2"), no? I'd expect this to also happen on SSE4.1 (also has 128bit NT loads).
> 
Yes, it's just the comment that needs fixing - !hasInt256() will already handle all SSE/AVX1 CPUs


Repository:
  rL LLVM

https://reviews.llvm.org/D33728