[PATCH] D33860: [AMDGPU] Untangle SDWA pass from SIShrinkInstructions

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: lib/Target/AMDGPU/SIPeepholeSDWA.cpp:617
+  int Opc32 = AMDGPU::getVOPe32(Opc);
+  if (Opc32 != -1 && AMDGPU::getSDWAOp(Opc32) != -1)
+    return true;
----------------
SamWot wrote:
> This check isn't strong enough. E.g. VOP3 (e64) instructions allow OMod that is not allowed in SDWA on VI.
> Another problem is SDST operand.  E.g. this is a valid instruction: v_add_i32_e64 v0, s[0:1], v1, v2. It writes carry-out into s[0:1] instead of VCC.
> Same problem can be with VOPC version of VOP3.
> You should either check for SDST operand or add special legalizer for it.
The VOPC is checked down in the convertToSDWA, but in general checks for omod and sdst are needed here. I will add them.


Repository:
  rL LLVM

https://reviews.llvm.org/D33860