[PATCH] D33114: [AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests.

[Mark Searles via Phabricator via llvm-commits]

msearles updated this revision to Diff 100486.
msearles added a comment.

Updates since last set of diffs:

- Fix conditional in SIInsertWaitCnts::updateEventWaitCntAfter() , which was always returning true
- Tweak how DS_PERMUTE/DS_SWIZZLE ops are modeled to cover issue found during RADV testing
- Tweak how new pass inserts waitcnts at the beginning/end of functions to match what old pass does
- Adjust existing tests
- Add new test ( test/CodeGen/AMDGPU/waitcnt-permute.mir ) to cover issue found during RADV testing


https://reviews.llvm.org/D33114

Files:
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/DSInstructions.td
  lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  test/CodeGen/AMDGPU/basic-branch.ll
  test/CodeGen/AMDGPU/branch-condition-and.ll
  test/CodeGen/AMDGPU/branch-relaxation.ll
  test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  test/CodeGen/AMDGPU/indirect-addressing-si.ll
  test/CodeGen/AMDGPU/infinite-loop.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.image.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
  test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
  test/CodeGen/AMDGPU/ret_jump.ll
  test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
  test/CodeGen/AMDGPU/smrd-vccz-bug.ll
  test/CodeGen/AMDGPU/spill-m0.ll
  test/CodeGen/AMDGPU/valu-i1.ll
  test/CodeGen/AMDGPU/waitcnt-permute.mir

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