[llvm] r303931 - [PPC] Fix atomics lowering in DAG lowering.

[Eric Christopher via llvm-commits]

On Thu, May 25, 2017 at 3:58 PM Tim Shen via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> Author: timshen
> Date: Thu May 25 17:58:35 2017
> New Revision: 303931
>
> URL: http://llvm.org/viewvc/llvm-project?rev=303931&view=rev
> Log:
> [PPC] Fix atomics lowering in DAG lowering.
>
> I forgot to forward the chain, causing some missing instruction
> dependencies. The test crashes the compiler without this patch.
>
> Inspired by the test case, D33519 also tries to remove the extra sync.
>
> Differential Revision: https://reviews.llvm.org/D33573
>
> Added:
>     llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll
> Modified:
>     llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=303931&r1=303930&r2=303931&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu May 25 17:58:35
> 2017
> @@ -8296,10 +8296,12 @@ SDValue PPCTargetLowering::LowerINTRINSI
>    SDLoc DL(Op);
>    switch (cast<ConstantSDNode>(Op.getOperand(ArgStart))->getZExtValue()) {
>    case Intrinsic::ppc_cfence: {
> +    assert(ArgStart == 1);
>

Assert needs text. :)

-eric


>      assert(Subtarget.isPPC64() && "Only 64-bit is supported for now.");
>      return SDValue(DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other,
>                                        DAG.getNode(ISD::ANY_EXTEND, DL,
> MVT::i64,
> -                                                  Op.getOperand(ArgStart
> + 1))),
> +                                                  Op.getOperand(ArgStart
> + 1)),
> +                                      Op.getOperand(0)),
>                     0);
>    }
>    default:
>
> Added: llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll?rev=303931&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll Thu May 25
> 17:58:35 2017
> @@ -0,0 +1,23 @@
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> +; RUN: llc < %s | FileCheck %s
> +
> +target triple = "powerpc64le-unknown-linux-gnu"
> +
> + at a = constant i64 zeroinitializer
> +
> +define i64 @foo() {
> +; CHECK-LABEL: foo:
> +; CHECK:       # BB#0: # %entry
> +; CHECK-NEXT:    addis 3, 2, .LC0 at toc@ha
> +; CHECK-NEXT:    li 4, 0
> +; CHECK-NEXT:    ld 3, .LC0 at toc@l(3)
> +; CHECK-NEXT:    cmpw 7, 4, 4
> +; CHECK-NEXT:    ld 3, 0(3)
> +; CHECK-NEXT:    bne- 7, .+4
> +; CHECK-NEXT:    isync
> +; CHECK-NEXT:    li 3, 0
> +; CHECK-NEXT:    blr
> +entry:
> +  %value = load atomic i64, i64* @a acquire, align 8
> +  ret i64 %value
> +}
>
>
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