[PATCH] D33442: [ARM] Fix lowering of misaligned memcpy/memset

[John Brawn via Phabricator via llvm-commits]

john.brawn updated this revision to Diff 100079.

Repository:
  rL LLVM

https://reviews.llvm.org/D33442

Files:
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  test/CodeGen/ARM/memcpy-inline.ll
  test/CodeGen/ARM/memset-inline.ll


Index: test/CodeGen/ARM/memset-inline.ll
===================================================================
--- test/CodeGen/ARM/memset-inline.ll
+++ test/CodeGen/ARM/memset-inline.ll
@@ -38,6 +38,32 @@
   ret void
 }
 
+define void @t3(i8* %p) {
+entry:
+; CHECK-7A-LABEL: t3:
+; CHECK-7A: muls [[REG:r[0-9]+]],
+; CHECK-7A: str  [[REG]],
+; CHECK-6M-LABEL: t3:
+; CHECK-6M-NOT: muls
+; CHECK-6M: strb [[REG:r[0-9]+]],
+; CHECK-6M: strb [[REG]],
+; CHECK-6M: strb [[REG]],
+; CHECK-6M: strb [[REG]],
+  br label %for.body
+
+for.body:
+  %i = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %0 = trunc i32 %i to i8
+  call void @llvm.memset.p0i8.i32(i8* %p, i8 %0, i32 4, i32 1, i1 false)
+  call void @something(i8* %p)
+  %inc = add nuw nsw i32 %i, 1
+  %exitcond = icmp eq i32 %inc, 255
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 declare void @something(i8*) nounwind
 declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
Index: test/CodeGen/ARM/memcpy-inline.ll
===================================================================
--- test/CodeGen/ARM/memcpy-inline.ll
+++ test/CodeGen/ARM/memcpy-inline.ll
@@ -95,10 +95,7 @@
 ; CHECK: movt [[REG7:r[0-9]+]], #22866
 ; CHECK: str [[REG7]]
 ; CHECK-T1-LABEL: t5:
-; CHECK-T1: movs [[TREG3:r[0-9]]],
-; CHECK-T1: strb [[TREG3]],
-; CHECK-T1: movs [[TREG4:r[0-9]]],
-; CHECK-T1: strb [[TREG4]],
+; CHECK-T1: bl _memcpy
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false)
   ret void
 }
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -12147,12 +12147,6 @@
     }
   }
 
-  // Lowering to i32/i16 if the size permits.
-  if (Size >= 4)
-    return MVT::i32;
-  else if (Size >= 2)
-    return MVT::i16;
-
   // Let the target-independent logic figure it out.
   return MVT::Other;
 }
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4779,9 +4779,10 @@
                                    DAG.getMachineFunction());
 
   if (VT == MVT::Other) {
+    EVT PointerVT = TLI.getPointerTy(DAG.getDataLayout(), DstAS);
     if (DstAlign >= DAG.getDataLayout().getPointerPrefAlignment(DstAS) ||
-        TLI.allowsMisalignedMemoryAccesses(VT, DstAS, DstAlign)) {
-      VT = TLI.getPointerTy(DAG.getDataLayout(), DstAS);
+        TLI.allowsMisalignedMemoryAccesses(PointerVT, DstAS, DstAlign)) {
+      VT = PointerVT;
     } else {
       switch (DstAlign & 7) {
       case 0:  VT = MVT::i64; break;


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