[PATCH] D33120: [ARM] Add VLDx/VSTx sched defs for machine-schedulers. NFCI.

[Javed Absar via Phabricator via llvm-commits]

javed.absar added a comment.

Hi Renato:
It depends a bit on how much 'special features' the sub-target pipeline  has. In some cases, just defining WriteRes to associate resource and latency etc with each SchedWrite type could suffice (e.g. for the Cortex-R52 the default WriteVLDx is sufficient).

For VSTx, unfortunately you will notice that things are bit different -  e.g. R52Read_F2 which has a ReadAdvance of +2 and the default Sched in ARMInstrNEON.td  does not capture it. 
One could annotate further SchedRead types  in ARMInstrNEON.td to capture this, but I think that would make it unnecessarily too detailed there.
Best Regards
--Javed


https://reviews.llvm.org/D33120