[PATCH] D32916: [DAGCombine] (addcarry 0, 0, X) -> (ext/trunc X)

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix added a comment.

I looked at the codegen for the mul and it looks correct. There are very little actual changes, but, they do cause registers to be allocated differently, so the diff ends up being huge.


https://reviews.llvm.org/D32916