[llvm] r303319 - Update three tests I missed in r302979 and r302990
Justin Bogner via llvm-commits
llvm-commits at lists.llvm.org
Wed May 17 17:58:06 PDT 2017
Author: bogner
Date: Wed May 17 19:58:06 2017
New Revision: 303319
URL: http://llvm.org/viewvc/llvm-project?rev=303319&view=rev
Log:
Update three tests I missed in r302979 and r302990
Added:
llvm/trunk/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
- copied, changed from r303318, llvm/trunk/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll
llvm/trunk/test/Transforms/InstCombine/NVPTX/
llvm/trunk/test/Transforms/InstCombine/NVPTX/lit.local.cfg
llvm/trunk/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll
- copied, changed from r303318, llvm/trunk/test/Transforms/InstCombine/nvvm-intrins.ll
Removed:
llvm/trunk/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll
llvm/trunk/test/Transforms/InstCombine/nvvm-intrins.ll
Modified:
llvm/trunk/test/Instrumentation/MemorySanitizer/csr.ll
Modified: llvm/trunk/test/Instrumentation/MemorySanitizer/csr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Instrumentation/MemorySanitizer/csr.ll?rev=303319&r1=303318&r2=303319&view=diff
==============================================================================
--- llvm/trunk/test/Instrumentation/MemorySanitizer/csr.ll (original)
+++ llvm/trunk/test/Instrumentation/MemorySanitizer/csr.ll Wed May 17 19:58:06 2017
@@ -1,5 +1,6 @@
; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
; RUN: opt < %s -msan -msan-check-access-address=1 -S | FileCheck %s --check-prefix=ADDR
+; REQUIRES: x86
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
Copied: llvm/trunk/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll (from r303318, llvm/trunk/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll?p2=llvm/trunk/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll&p1=llvm/trunk/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll&r1=303318&r2=303319&rev=303319&view=diff
==============================================================================
(empty)
Added: llvm/trunk/test/Transforms/InstCombine/NVPTX/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/NVPTX/lit.local.cfg?rev=303319&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/NVPTX/lit.local.cfg (added)
+++ llvm/trunk/test/Transforms/InstCombine/NVPTX/lit.local.cfg Wed May 17 19:58:06 2017
@@ -0,0 +1,2 @@
+if not 'NVPTX' in config.root.targets:
+ config.unsupported = True
Copied: llvm/trunk/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll (from r303318, llvm/trunk/test/Transforms/InstCombine/nvvm-intrins.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll?p2=llvm/trunk/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll&p1=llvm/trunk/test/Transforms/InstCombine/nvvm-intrins.ll&r1=303318&r2=303319&rev=303319&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll?rev=303318&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll (removed)
@@ -1,1506 +0,0 @@
-; RUN: opt -S -instcombine %s | FileCheck %s
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.buffer.load
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @buffer_load_f32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @buffer_load_f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- ret float %data
-}
-
-; CHECK-LABEL: @buffer_load_v1f32(
-; CHECK-NEXT: %data = call <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: ret <1 x float> %data
-define amdgpu_ps <1 x float> @buffer_load_v1f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- ret <1 x float> %data
-}
-
-; CHECK-LABEL: @buffer_load_v2f32(
-; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: ret <2 x float> %data
-define amdgpu_ps <2 x float> @buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- ret <2 x float> %data
-}
-
-; CHECK-LABEL: @buffer_load_v4f32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: ret <4 x float> %data
-define amdgpu_ps <4 x float> @buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- ret <4 x float> %data
-}
-
-; CHECK-LABEL: @extract_elt0_buffer_load_v2f32(
-; CHECK: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %elt0 = extractelement <2 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt1_buffer_load_v2f32(
-; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
-; CHECK-NEXT: ret float %elt1
-define amdgpu_ps float @extract_elt1_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %elt1 = extractelement <2 x float> %data, i32 1
- ret float %elt1
-}
-
-; CHECK-LABEL: @extract_elt0_buffer_load_v4f32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt1_buffer_load_v4f32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %elt1 = extractelement <4 x float> %data, i32 1
-; CHECK-NEXT: ret float %elt1
-define amdgpu_ps float @extract_elt1_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %elt1 = extractelement <4 x float> %data, i32 1
- ret float %elt1
-}
-
-; CHECK-LABEL: @extract_elt2_buffer_load_v4f32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %elt1 = extractelement <4 x float> %data, i32 2
-; CHECK-NEXT: ret float %elt1
-define amdgpu_ps float @extract_elt2_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %elt1 = extractelement <4 x float> %data, i32 2
- ret float %elt1
-}
-
-; CHECK-LABEL: @extract_elt3_buffer_load_v4f32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %elt1 = extractelement <4 x float> %data, i32 3
-; CHECK-NEXT: ret float %elt1
-define amdgpu_ps float @extract_elt3_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %elt1 = extractelement <4 x float> %data, i32 3
- ret float %elt1
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_buffer_load_v4f32(
-; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: ret <2 x float>
-define amdgpu_ps <2 x float> @extract_elt0_elt1_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
- ret <2 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt1_elt2_buffer_load_v4f32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
-; CHECK-NEXT: ret <2 x float> %shuf
-define amdgpu_ps <2 x float> @extract_elt1_elt2_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
- ret <2 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt2_elt3_buffer_load_v4f32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT: ret <2 x float> %shuf
-define amdgpu_ps <2 x float> @extract_elt2_elt3_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
- ret <2 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
-; CHECK-NEXT: ret <3 x float> %shuf
-define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
- ret <3 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt1_elt2_elt3_buffer_load_v4f32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
-; CHECK-NEXT: ret <3 x float> %shuf
-define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
- ret <3 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt0_elt2_elt3_buffer_load_v4f32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
-; CHECK-NEXT: ret <3 x float> %shuf
-define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
- ret <3 x float> %shuf
-}
-
-; FIXME: Not handled even though only 2 elts used
-; CHECK-LABEL: @extract_elt0_elt1_buffer_load_v4f32_2(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %elt0 = extractelement <4 x float> %data, i32 0
-; CHECK-NEXT: %elt1 = extractelement <4 x float> %data, i32 1
-; CHECK-NEXT: %ins0 = insertvalue { float, float } undef, float %elt0, 0
-; CHECK-NEXT: %ins1 = insertvalue { float, float } %ins0, float %elt1, 1
-; CHECK-NEXT: ret { float, float } %ins1
-define amdgpu_ps { float, float } @extract_elt0_elt1_buffer_load_v4f32_2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- %elt1 = extractelement <4 x float> %data, i32 1
- %ins0 = insertvalue { float, float } undef, float %elt0, 0
- %ins1 = insertvalue { float, float } %ins0, float %elt1, 1
- ret { float, float } %ins1
-}
-
-; CHECK-LABEL: @extract_elt0_buffer_load_v3f32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %elt0 = extractelement <3 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt1_buffer_load_v3f32(
-; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 1
-; CHECK-NEXT: ret float %elt1
-define amdgpu_ps float @extract_elt1_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %elt1 = extractelement <3 x float> %data, i32 1
- ret float %elt1
-}
-
-; CHECK-LABEL: @extract_elt2_buffer_load_v3f32(
-; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
-; CHECK-NEXT: ret float %elt1
-define amdgpu_ps float @extract_elt2_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %elt1 = extractelement <3 x float> %data, i32 2
- ret float %elt1
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_buffer_load_v3f32(
-; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: ret <2 x float>
-define amdgpu_ps <2 x float> @extract_elt0_elt1_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
- ret <2 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt1_elt2_buffer_load_v3f32(
-; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
-; CHECK-NEXT: ret <2 x float> %shuf
-define amdgpu_ps <2 x float> @extract_elt1_elt2_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
- ret <2 x float> %shuf
-}
-
-; CHECK-LABEL: @preserve_metadata_extract_elt0_buffer_load_v2f32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false), !fpmath !0
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @preserve_metadata_extract_elt0_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false), !fpmath !0
- %elt0 = extractelement <2 x float> %data, i32 0
- ret float %elt0
-}
-
-declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.buffer.load.format
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @buffer_load_format_v1f32(
-; CHECK-NEXT: %data = call <1 x float> @llvm.amdgcn.buffer.load.format.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 true)
-; CHECK-NEXT: ret <1 x float> %data
-define amdgpu_ps <1 x float> @buffer_load_format_v1f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <1 x float> @llvm.amdgcn.buffer.load.format.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 true)
- ret <1 x float> %data
-}
-
-; CHECK-LABEL: @extract_elt0_buffer_load_format_v2f32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 true, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_buffer_load_format_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 true, i1 false)
- %elt0 = extractelement <2 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_buffer_load_format_v3f32(
-; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: ret <2 x float> %data
-define amdgpu_ps <2 x float> @extract_elt0_elt1_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
- ret <2 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_buffer_load_format_v4f32(
-; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
-; CHECK-NEXT: ret <2 x float> %data
-define amdgpu_ps <2 x float> @extract_elt0_elt1_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
- %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
- ret <2 x float> %shuf
-}
-
-; The initial insertion point is at the extractelement
-; CHECK-LABEL: @extract01_bitcast_buffer_load_format_v4f32(
-; CHECK-NEXT: %tmp = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false)
-; CHECK-NEXT: %1 = shufflevector <2 x float> %tmp, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
-; CHECK-NEXT: %tmp1 = bitcast <4 x float> %1 to <2 x double>
-; CHECK-NEXT: %tmp2 = extractelement <2 x double> %tmp1, i32 0
-; CHECK-NEXT: ret double %tmp2
-define double @extract01_bitcast_buffer_load_format_v4f32(i32 %arg) #0 {
- %tmp = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false) #3
- %tmp1 = bitcast <4 x float> %tmp to <2 x double>
- %tmp2 = extractelement <2 x double> %tmp1, i32 0
- ret double %tmp2
-}
-
-; CHECK-LABEL: @extract0_bitcast_buffer_load_format_v4f32(
-; CHECK-NEXT: %tmp = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false)
-; CHECK-NEXT: %tmp2 = bitcast float %tmp to i32
-; CHECK-NEXT: ret i32 %tmp2
-define i32 @extract0_bitcast_buffer_load_format_v4f32(i32 %arg) #0 {
- %tmp = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false) #3
- %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
- %tmp2 = extractelement <4 x i32> %tmp1, i32 0
- ret i32 %tmp2
-}
-
-; CHECK-LABEL: @extract_lo16_0_bitcast_buffer_load_format_v4f32(
-; CHECK-NEXT: %tmp = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false)
-; CHECK-NEXT: %1 = insertelement <4 x float> undef, float %tmp, i64 0
-; CHECK-NEXT: %tmp1 = bitcast <4 x float> %1 to <8 x i16>
-; CHECK-NEXT: %tmp2 = extractelement <8 x i16> %tmp1, i32 0
-; CHECK-NEXT: ret i16 %tmp2
-define i16 @extract_lo16_0_bitcast_buffer_load_format_v4f32(i32 %arg) #0 {
- %tmp = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false) #3
- %tmp1 = bitcast <4 x float> %tmp to <8 x i16>
- %tmp2 = extractelement <8 x i16> %tmp1, i32 0
- ret i16 %tmp2
-}
-
-declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <1 x float> @llvm.amdgcn.buffer.load.format.v1f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_sample_v4f32_v4f32_v4i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_sample_v4f32_v2f32_v4i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_invalid_dmask_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 %dmask, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_invalid_dmask_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc, i32 %dmask) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 %dmask, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; FIXME: Should really fold to undef
-; CHECK-LABEL: @extract_elt0_dmask_0000_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_dmask_0000_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_dmask_0001_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_dmask_0001_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; FIXME: Should really fold to undef
-; CHECK-LABEL: @extract_elt0_dmask_0010_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 2, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_dmask_0010_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 2, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; FIXME: Should really fold to undef
-; CHECK-LABEL: @extract_elt0_dmask_0100_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 4, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_dmask_0100_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 4, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; FIXME: Should really fold to undef
-; CHECK-LABEL: @extract_elt0_dmask_1000_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 8, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_dmask_1000_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 8, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_dmask_1001_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_dmask_1001_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 9, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_dmask_0011_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_dmask_0011_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_dmask_0111_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_dmask_0111_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 7, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_dmask_0001_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.v2f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret <2 x float> %data
-define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0001_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
- ret <2 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_dmask_0011_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.v2f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret <2 x float> %data
-define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0011_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
- ret <2 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_dmask_0111_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.v2f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret <2 x float> %data
-define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0111_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 7, i1 false, i1 false, i1 false, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
- ret <2 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_dmask_0101_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.v2f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 5, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret <2 x float> %data
-define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0101_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 5, i1 false, i1 false, i1 false, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
- ret <2 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0001_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
-; CHECK-NEXT: ret <3 x float> %shuf
-define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0001_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
- ret <3 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0011_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
-; CHECK-NEXT: ret <3 x float> %shuf
-define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0011_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
- ret <3 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0101_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 5, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
-; CHECK-NEXT: ret <3 x float> %shuf
-define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0101_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 5, i1 false, i1 false, i1 false, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
- ret <3 x float> %shuf
-}
-
-; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0111_image_sample_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 7, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
-; CHECK-NEXT: ret <3 x float> %shuf
-define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0111_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 7, i1 false, i1 false, i1 false, i1 false, i1 false)
- %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
- ret <3 x float> %shuf
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.cl
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_cl_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.d
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_d_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_d_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.d.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.d.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.d.cl
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_d_cl_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_d_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.d.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.d.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.l
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_l_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.l.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_l_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.l.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.l.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.b
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_b_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.b.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_b_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.b.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.b.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.b.cl
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_b_cl_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.b.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_b_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.b.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.b.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.lz
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_lz_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.lz.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_lz_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.lz.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.lz.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.cd
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_cd_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cd.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_cd_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.cd.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.cd.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.cd.cl
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_cd_cl_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cd.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_cd_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_v4f32_v4f32_v4i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_v4f32_v2f32_v4i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.cl
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_cl_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.d
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_d_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_d_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.d.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.d.cl
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_d_cl_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_d_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.l
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_l_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.l.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_l_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.l.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.l.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.b
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_b_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_b_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.b.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.b.cl
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_b_cl_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_b_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.lz
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_lz_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.lz.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_lz_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.lz.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.lz.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.cd
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_cd_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_cd_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.cd.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.cd.cl
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_cd_cl_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_cd_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_sample_o_v4f32_v4f32_v4i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.o.f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_o_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_sample_o_v4f32_v2f32_v4i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.o.f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_o_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.d.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_d_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_d_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.d.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.d.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.d.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_d_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_d_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.d.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.d.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.l.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_l_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.l.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_l_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.l.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.b.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_b_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.b.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_b_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.b.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.b.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_b_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.b.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_b_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.b.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.lz.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_lz_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.lz.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_lz_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.lz.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.cd.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_cd_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cd.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_cd_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.cd.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.cd.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.cd.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_cd_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cd.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_cd_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_o_v4f32_v4f32_v4i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.o.f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_o_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_o_v4f32_v2f32_v4i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.o.f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_o_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.d.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_d_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_d_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.d.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.d.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_d_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_d_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.l.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_l_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.l.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_l_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.l.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.b.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_b_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_b_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.b.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_b_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_b_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.lz.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_lz_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.lz.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_lz_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.lz.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.cd.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_cd_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_cd_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.cd.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.sample.c.cd.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_sample_c_cd_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_sample_c_cd_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4
-; --------------------------------------------------------------------
-
-; Don't handle gather4*
-
-; CHECK-LABEL: @extract_elt0_image_gather4_v4f32_v4f32_v8i32(
-; CHECK: %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i3
-define amdgpu_ps float @extract_elt0_image_gather4_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_gather4_v4f32_v4f32_v4i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_gather4_v4f32_v2f32_v4i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.gather4.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.cl
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_cl_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.l
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_l_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.l.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_l_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.l.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.l.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.b
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_b_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_b_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.b.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.b.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.b.cl
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_b_cl_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_b_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.lz
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_lz_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_lz_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_gather4_o_v4f32_v4f32_v4i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_o_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_gather4_o_v4f32_v2f32_v4i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_o_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.l.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_l_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_l_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.l.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.b.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_b_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_b_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.b.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.b.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_b_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_b_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.lz.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_lz_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_lz_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.lz.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.c.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_c_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_c_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_gather4_c_o_v4f32_v4f32_v4i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_c_o_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_gather4_c_o_v4f32_v2f32_v4i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_c_o_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.c.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_c_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_c_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.c.l.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_c_l_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_c_l_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.c.l.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.c.b.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_c_b_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_c_b_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.c.b.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.c.b.cl.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_c_b_cl_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_c_b_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.gather4.c.lz.o
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_gather4_c_lz_o_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
-define amdgpu_ps float @extract_elt0_image_gather4_c_lz_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.image.getlod
-; --------------------------------------------------------------------
-
-; CHECK-LABEL: @extract_elt0_image_getlod_v4f32_v4f32_v8i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.getlod.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_getlod_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.getlod.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_getlod_v4f32_v4f32_v4i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.getlod.f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_getlod_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.getlod.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-; CHECK-LABEL: @extract_elt0_image_getlod_v4f32_v2f32_v4i32(
-; CHECK-NEXT: %data = call float @llvm.amdgcn.image.getlod.f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
-; CHECK-NEXT: ret float %data
-define amdgpu_ps float @extract_elt0_image_getlod_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
- %data = call <4 x float> @llvm.amdgcn.image.getlod.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
- %elt0 = extractelement <4 x float> %data, i32 0
- ret float %elt0
-}
-
-declare <4 x float> @llvm.amdgcn.image.getlod.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.getlod.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.image.getlod.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readonly }
-
-!0 = !{float 2.500000e+00}
Removed: llvm/trunk/test/Transforms/InstCombine/nvvm-intrins.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/nvvm-intrins.ll?rev=303318&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/nvvm-intrins.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/nvvm-intrins.ll (removed)
@@ -1,471 +0,0 @@
-; Check that nvvm intrinsics get simplified to target-generic intrinsics where
-; possible.
-;
-; We run this test twice; once with ftz on, and again with ftz off. Behold the
-; hackery:
-
-; RUN: cat %s > %t.ftz
-; RUN: echo 'attributes #0 = { "nvptx-f32ftz" = "true" }' >> %t.ftz
-; RUN: opt < %t.ftz -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=FTZ
-
-; RUN: cat %s > %t.noftz
-; RUN: echo 'attributes #0 = { "nvptx-f32ftz" = "false" }' >> %t.noftz
-; RUN: opt < %t.noftz -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=NOFTZ
-
-; We handle nvvm intrinsics with ftz variants as follows:
-; - If the module is in ftz mode, the ftz variant is transformed into the
-; regular llvm intrinsic, and the non-ftz variant is left alone.
-; - If the module is not in ftz mode, it's the reverse: Only the non-ftz
-; variant is transformed, and the ftz variant is left alone.
-
-; Check NVVM intrinsics that map directly to LLVM target-generic intrinsics.
-
-; CHECK-LABEL: @ceil_double
-define double @ceil_double(double %a) #0 {
-; CHECK: call double @llvm.ceil.f64
- %ret = call double @llvm.nvvm.ceil.d(double %a)
- ret double %ret
-}
-; CHECK-LABEL: @ceil_float
-define float @ceil_float(float %a) #0 {
-; NOFTZ: call float @llvm.ceil.f32
-; FTZ: call float @llvm.nvvm.ceil.f
- %ret = call float @llvm.nvvm.ceil.f(float %a)
- ret float %ret
-}
-; CHECK-LABEL: @ceil_float_ftz
-define float @ceil_float_ftz(float %a) #0 {
-; NOFTZ: call float @llvm.nvvm.ceil.ftz.f
-; FTZ: call float @llvm.ceil.f32
- %ret = call float @llvm.nvvm.ceil.ftz.f(float %a)
- ret float %ret
-}
-
-; CHECK-LABEL: @fabs_double
-define double @fabs_double(double %a) #0 {
-; CHECK: call double @llvm.fabs.f64
- %ret = call double @llvm.nvvm.fabs.d(double %a)
- ret double %ret
-}
-; CHECK-LABEL: @fabs_float
-define float @fabs_float(float %a) #0 {
-; NOFTZ: call float @llvm.fabs.f32
-; FTZ: call float @llvm.nvvm.fabs.f
- %ret = call float @llvm.nvvm.fabs.f(float %a)
- ret float %ret
-}
-; CHECK-LABEL: @fabs_float_ftz
-define float @fabs_float_ftz(float %a) #0 {
-; NOFTZ: call float @llvm.nvvm.fabs.ftz.f
-; FTZ: call float @llvm.fabs.f32
- %ret = call float @llvm.nvvm.fabs.ftz.f(float %a)
- ret float %ret
-}
-
-; CHECK-LABEL: @floor_double
-define double @floor_double(double %a) #0 {
-; CHECK: call double @llvm.floor.f64
- %ret = call double @llvm.nvvm.floor.d(double %a)
- ret double %ret
-}
-; CHECK-LABEL: @floor_float
-define float @floor_float(float %a) #0 {
-; NOFTZ: call float @llvm.floor.f32
-; FTZ: call float @llvm.nvvm.floor.f
- %ret = call float @llvm.nvvm.floor.f(float %a)
- ret float %ret
-}
-; CHECK-LABEL: @floor_float_ftz
-define float @floor_float_ftz(float %a) #0 {
-; NOFTZ: call float @llvm.nvvm.floor.ftz.f
-; FTZ: call float @llvm.floor.f32
- %ret = call float @llvm.nvvm.floor.ftz.f(float %a)
- ret float %ret
-}
-
-; CHECK-LABEL: @fma_double
-define double @fma_double(double %a, double %b, double %c) #0 {
-; CHECK: call double @llvm.fma.f64
- %ret = call double @llvm.nvvm.fma.rn.d(double %a, double %b, double %c)
- ret double %ret
-}
-; CHECK-LABEL: @fma_float
-define float @fma_float(float %a, float %b, float %c) #0 {
-; NOFTZ: call float @llvm.fma.f32
-; FTZ: call float @llvm.nvvm.fma.rn.f
- %ret = call float @llvm.nvvm.fma.rn.f(float %a, float %b, float %c)
- ret float %ret
-}
-; CHECK-LABEL: @fma_float_ftz
-define float @fma_float_ftz(float %a, float %b, float %c) #0 {
-; NOFTZ: call float @llvm.nvvm.fma.rn.ftz.f
-; FTZ: call float @llvm.fma.f32
- %ret = call float @llvm.nvvm.fma.rn.ftz.f(float %a, float %b, float %c)
- ret float %ret
-}
-
-; CHECK-LABEL: @fmax_double
-define double @fmax_double(double %a, double %b) #0 {
-; CHECK: call double @llvm.maxnum.f64
- %ret = call double @llvm.nvvm.fmax.d(double %a, double %b)
- ret double %ret
-}
-; CHECK-LABEL: @fmax_float
-define float @fmax_float(float %a, float %b) #0 {
-; NOFTZ: call float @llvm.maxnum.f32
-; FTZ: call float @llvm.nvvm.fmax.f
- %ret = call float @llvm.nvvm.fmax.f(float %a, float %b)
- ret float %ret
-}
-; CHECK-LABEL: @fmax_float_ftz
-define float @fmax_float_ftz(float %a, float %b) #0 {
-; NOFTZ: call float @llvm.nvvm.fmax.ftz.f
-; FTZ: call float @llvm.maxnum.f32
- %ret = call float @llvm.nvvm.fmax.ftz.f(float %a, float %b)
- ret float %ret
-}
-
-; CHECK-LABEL: @fmin_double
-define double @fmin_double(double %a, double %b) #0 {
-; CHECK: call double @llvm.minnum.f64
- %ret = call double @llvm.nvvm.fmin.d(double %a, double %b)
- ret double %ret
-}
-; CHECK-LABEL: @fmin_float
-define float @fmin_float(float %a, float %b) #0 {
-; NOFTZ: call float @llvm.minnum.f32
-; FTZ: call float @llvm.nvvm.fmin.f
- %ret = call float @llvm.nvvm.fmin.f(float %a, float %b)
- ret float %ret
-}
-; CHECK-LABEL: @fmin_float_ftz
-define float @fmin_float_ftz(float %a, float %b) #0 {
-; NOFTZ: call float @llvm.nvvm.fmin.ftz.f
-; FTZ: call float @llvm.minnum.f32
- %ret = call float @llvm.nvvm.fmin.ftz.f(float %a, float %b)
- ret float %ret
-}
-
-; CHECK-LABEL: @round_double
-define double @round_double(double %a) #0 {
-; CHECK: call double @llvm.round.f64
- %ret = call double @llvm.nvvm.round.d(double %a)
- ret double %ret
-}
-; CHECK-LABEL: @round_float
-define float @round_float(float %a) #0 {
-; NOFTZ: call float @llvm.round.f32
-; FTZ: call float @llvm.nvvm.round.f
- %ret = call float @llvm.nvvm.round.f(float %a)
- ret float %ret
-}
-; CHECK-LABEL: @round_float_ftz
-define float @round_float_ftz(float %a) #0 {
-; NOFTZ: call float @llvm.nvvm.round.ftz.f
-; FTZ: call float @llvm.round.f32
- %ret = call float @llvm.nvvm.round.ftz.f(float %a)
- ret float %ret
-}
-
-; CHECK-LABEL: @trunc_double
-define double @trunc_double(double %a) #0 {
-; CHECK: call double @llvm.trunc.f64
- %ret = call double @llvm.nvvm.trunc.d(double %a)
- ret double %ret
-}
-; CHECK-LABEL: @trunc_float
-define float @trunc_float(float %a) #0 {
-; NOFTZ: call float @llvm.trunc.f32
-; FTZ: call float @llvm.nvvm.trunc.f
- %ret = call float @llvm.nvvm.trunc.f(float %a)
- ret float %ret
-}
-; CHECK-LABEL: @trunc_float_ftz
-define float @trunc_float_ftz(float %a) #0 {
-; NOFTZ: call float @llvm.nvvm.trunc.ftz.f
-; FTZ: call float @llvm.trunc.f32
- %ret = call float @llvm.nvvm.trunc.ftz.f(float %a)
- ret float %ret
-}
-
-; Check NVVM intrinsics that correspond to LLVM cast operations.
-
-; CHECK-LABEL: @test_d2i
-define i32 @test_d2i(double %a) #0 {
-; CHECK: fptosi double %a to i32
- %ret = call i32 @llvm.nvvm.d2i.rz(double %a)
- ret i32 %ret
-}
-; CHECK-LABEL: @test_f2i
-define i32 @test_f2i(float %a) #0 {
-; CHECK: fptosi float %a to i32
- %ret = call i32 @llvm.nvvm.f2i.rz(float %a)
- ret i32 %ret
-}
-; CHECK-LABEL: @test_d2ll
-define i64 @test_d2ll(double %a) #0 {
-; CHECK: fptosi double %a to i64
- %ret = call i64 @llvm.nvvm.d2ll.rz(double %a)
- ret i64 %ret
-}
-; CHECK-LABEL: @test_f2ll
-define i64 @test_f2ll(float %a) #0 {
-; CHECK: fptosi float %a to i64
- %ret = call i64 @llvm.nvvm.f2ll.rz(float %a)
- ret i64 %ret
-}
-; CHECK-LABEL: @test_d2ui
-define i32 @test_d2ui(double %a) #0 {
-; CHECK: fptoui double %a to i32
- %ret = call i32 @llvm.nvvm.d2ui.rz(double %a)
- ret i32 %ret
-}
-; CHECK-LABEL: @test_f2ui
-define i32 @test_f2ui(float %a) #0 {
-; CHECK: fptoui float %a to i32
- %ret = call i32 @llvm.nvvm.f2ui.rz(float %a)
- ret i32 %ret
-}
-; CHECK-LABEL: @test_d2ull
-define i64 @test_d2ull(double %a) #0 {
-; CHECK: fptoui double %a to i64
- %ret = call i64 @llvm.nvvm.d2ull.rz(double %a)
- ret i64 %ret
-}
-; CHECK-LABEL: @test_f2ull
-define i64 @test_f2ull(float %a) #0 {
-; CHECK: fptoui float %a to i64
- %ret = call i64 @llvm.nvvm.f2ull.rz(float %a)
- ret i64 %ret
-}
-
-; CHECK-LABEL: @test_i2d
-define double @test_i2d(i32 %a) #0 {
-; CHECK: sitofp i32 %a to double
- %ret = call double @llvm.nvvm.i2d.rz(i32 %a)
- ret double %ret
-}
-; CHECK-LABEL: @test_i2f
-define float @test_i2f(i32 %a) #0 {
-; CHECK: sitofp i32 %a to float
- %ret = call float @llvm.nvvm.i2f.rz(i32 %a)
- ret float %ret
-}
-; CHECK-LABEL: @test_ll2d
-define double @test_ll2d(i64 %a) #0 {
-; CHECK: sitofp i64 %a to double
- %ret = call double @llvm.nvvm.ll2d.rz(i64 %a)
- ret double %ret
-}
-; CHECK-LABEL: @test_ll2f
-define float @test_ll2f(i64 %a) #0 {
-; CHECK: sitofp i64 %a to float
- %ret = call float @llvm.nvvm.ll2f.rz(i64 %a)
- ret float %ret
-}
-; CHECK-LABEL: @test_ui2d
-define double @test_ui2d(i32 %a) #0 {
-; CHECK: uitofp i32 %a to double
- %ret = call double @llvm.nvvm.ui2d.rz(i32 %a)
- ret double %ret
-}
-; CHECK-LABEL: @test_ui2f
-define float @test_ui2f(i32 %a) #0 {
-; CHECK: uitofp i32 %a to float
- %ret = call float @llvm.nvvm.ui2f.rz(i32 %a)
- ret float %ret
-}
-; CHECK-LABEL: @test_ull2d
-define double @test_ull2d(i64 %a) #0 {
-; CHECK: uitofp i64 %a to double
- %ret = call double @llvm.nvvm.ull2d.rz(i64 %a)
- ret double %ret
-}
-; CHECK-LABEL: @test_ull2f
-define float @test_ull2f(i64 %a) #0 {
-; CHECK: uitofp i64 %a to float
- %ret = call float @llvm.nvvm.ull2f.rz(i64 %a)
- ret float %ret
-}
-
-; Check NVVM intrinsics that map to LLVM binary operations.
-
-; CHECK-LABEL: @test_add_rn_d
-define double @test_add_rn_d(double %a, double %b) #0 {
-; CHECK: fadd
- %ret = call double @llvm.nvvm.add.rn.d(double %a, double %b)
- ret double %ret
-}
-; CHECK-LABEL: @test_add_rn_f
-define float @test_add_rn_f(float %a, float %b) #0 {
-; NOFTZ: fadd
-; FTZ: call float @llvm.nvvm.add.rn.f
- %ret = call float @llvm.nvvm.add.rn.f(float %a, float %b)
- ret float %ret
-}
-; CHECK-LABEL: @test_add_rn_f_ftz
-define float @test_add_rn_f_ftz(float %a, float %b) #0 {
-; NOFTZ: call float @llvm.nvvm.add.rn.f
-; FTZ: fadd
- %ret = call float @llvm.nvvm.add.rn.ftz.f(float %a, float %b)
- ret float %ret
-}
-
-; CHECK-LABEL: @test_mul_rn_d
-define double @test_mul_rn_d(double %a, double %b) #0 {
-; CHECK: fmul
- %ret = call double @llvm.nvvm.mul.rn.d(double %a, double %b)
- ret double %ret
-}
-; CHECK-LABEL: @test_mul_rn_f
-define float @test_mul_rn_f(float %a, float %b) #0 {
-; NOFTZ: fmul
-; FTZ: call float @llvm.nvvm.mul.rn.f
- %ret = call float @llvm.nvvm.mul.rn.f(float %a, float %b)
- ret float %ret
-}
-; CHECK-LABEL: @test_mul_rn_f_ftz
-define float @test_mul_rn_f_ftz(float %a, float %b) #0 {
-; NOFTZ: call float @llvm.nvvm.mul.rn.f
-; FTZ: fmul
- %ret = call float @llvm.nvvm.mul.rn.ftz.f(float %a, float %b)
- ret float %ret
-}
-
-; CHECK-LABEL: @test_div_rn_d
-define double @test_div_rn_d(double %a, double %b) #0 {
-; CHECK: fdiv
- %ret = call double @llvm.nvvm.div.rn.d(double %a, double %b)
- ret double %ret
-}
-; CHECK-LABEL: @test_div_rn_f
-define float @test_div_rn_f(float %a, float %b) #0 {
-; NOFTZ: fdiv
-; FTZ: call float @llvm.nvvm.div.rn.f
- %ret = call float @llvm.nvvm.div.rn.f(float %a, float %b)
- ret float %ret
-}
-; CHECK-LABEL: @test_div_rn_f_ftz
-define float @test_div_rn_f_ftz(float %a, float %b) #0 {
-; NOFTZ: call float @llvm.nvvm.div.rn.f
-; FTZ: fdiv
- %ret = call float @llvm.nvvm.div.rn.ftz.f(float %a, float %b)
- ret float %ret
-}
-
-; Check NVVM intrinsics that require us to emit custom IR.
-
-; CHECK-LABEL: @test_rcp_rn_f
-define float @test_rcp_rn_f(float %a) #0 {
-; NOFTZ: fdiv float 1.0{{.*}} %a
-; FTZ: call float @llvm.nvvm.rcp.rn.f
- %ret = call float @llvm.nvvm.rcp.rn.f(float %a)
- ret float %ret
-}
-; CHECK-LABEL: @test_rcp_rn_f_ftz
-define float @test_rcp_rn_f_ftz(float %a) #0 {
-; NOFTZ: call float @llvm.nvvm.rcp.rn.f
-; FTZ: fdiv float 1.0{{.*}} %a
- %ret = call float @llvm.nvvm.rcp.rn.ftz.f(float %a)
- ret float %ret
-}
-
-; CHECK-LABEL: @test_sqrt_rn_d
-define double @test_sqrt_rn_d(double %a) #0 {
-; CHECK: call double @llvm.sqrt.f64(double %a)
- %ret = call double @llvm.nvvm.sqrt.rn.d(double %a)
- ret double %ret
-}
-; nvvm.sqrt.f is a special case: It goes to a llvm.sqrt.f
-; CHECK-LABEL: @test_sqrt_f
-define float @test_sqrt_f(float %a) #0 {
-; CHECK: call float @llvm.sqrt.f32(float %a)
- %ret = call float @llvm.nvvm.sqrt.f(float %a)
- ret float %ret
-}
-; CHECK-LABEL: @test_sqrt_rn_f
-define float @test_sqrt_rn_f(float %a) #0 {
-; NOFTZ: call float @llvm.sqrt.f32(float %a)
-; FTZ: call float @llvm.nvvm.sqrt.rn.f
- %ret = call float @llvm.nvvm.sqrt.rn.f(float %a)
- ret float %ret
-}
-; CHECK-LABEL: @test_sqrt_rn_f_ftz
-define float @test_sqrt_rn_f_ftz(float %a) #0 {
-; NOFTZ: call float @llvm.nvvm.sqrt.rn.f
-; FTZ: call float @llvm.sqrt.f32(float %a)
- %ret = call float @llvm.nvvm.sqrt.rn.ftz.f(float %a)
- ret float %ret
-}
-
-declare double @llvm.nvvm.add.rn.d(double, double)
-declare float @llvm.nvvm.add.rn.f(float, float)
-declare float @llvm.nvvm.add.rn.ftz.f(float, float)
-declare double @llvm.nvvm.ceil.d(double)
-declare float @llvm.nvvm.ceil.f(float)
-declare float @llvm.nvvm.ceil.ftz.f(float)
-declare float @llvm.nvvm.d2f.rm(double)
-declare float @llvm.nvvm.d2f.rm.ftz(double)
-declare float @llvm.nvvm.d2f.rp(double)
-declare float @llvm.nvvm.d2f.rp.ftz(double)
-declare float @llvm.nvvm.d2f.rz(double)
-declare float @llvm.nvvm.d2f.rz.ftz(double)
-declare i32 @llvm.nvvm.d2i.rz(double)
-declare i64 @llvm.nvvm.d2ll.rz(double)
-declare i32 @llvm.nvvm.d2ui.rz(double)
-declare i64 @llvm.nvvm.d2ull.rz(double)
-declare double @llvm.nvvm.div.rn.d(double, double)
-declare float @llvm.nvvm.div.rn.f(float, float)
-declare float @llvm.nvvm.div.rn.ftz.f(float, float)
-declare i16 @llvm.nvvm.f2h.rz(float)
-declare i16 @llvm.nvvm.f2h.rz.ftz(float)
-declare i32 @llvm.nvvm.f2i.rz(float)
-declare i32 @llvm.nvvm.f2i.rz.ftz(float)
-declare i64 @llvm.nvvm.f2ll.rz(float)
-declare i64 @llvm.nvvm.f2ll.rz.ftz(float)
-declare i32 @llvm.nvvm.f2ui.rz(float)
-declare i32 @llvm.nvvm.f2ui.rz.ftz(float)
-declare i64 @llvm.nvvm.f2ull.rz(float)
-declare i64 @llvm.nvvm.f2ull.rz.ftz(float)
-declare double @llvm.nvvm.fabs.d(double)
-declare float @llvm.nvvm.fabs.f(float)
-declare float @llvm.nvvm.fabs.ftz.f(float)
-declare double @llvm.nvvm.floor.d(double)
-declare float @llvm.nvvm.floor.f(float)
-declare float @llvm.nvvm.floor.ftz.f(float)
-declare double @llvm.nvvm.fma.rn.d(double, double, double)
-declare float @llvm.nvvm.fma.rn.f(float, float, float)
-declare float @llvm.nvvm.fma.rn.ftz.f(float, float, float)
-declare double @llvm.nvvm.fmax.d(double, double)
-declare float @llvm.nvvm.fmax.f(float, float)
-declare float @llvm.nvvm.fmax.ftz.f(float, float)
-declare double @llvm.nvvm.fmin.d(double, double)
-declare float @llvm.nvvm.fmin.f(float, float)
-declare float @llvm.nvvm.fmin.ftz.f(float, float)
-declare double @llvm.nvvm.i2d.rz(i32)
-declare float @llvm.nvvm.i2f.rz(i32)
-declare double @llvm.nvvm.ll2d.rz(i64)
-declare float @llvm.nvvm.ll2f.rz(i64)
-declare double @llvm.nvvm.lohi.i2d(i32, i32)
-declare double @llvm.nvvm.mul.rn.d(double, double)
-declare float @llvm.nvvm.mul.rn.f(float, float)
-declare float @llvm.nvvm.mul.rn.ftz.f(float, float)
-declare double @llvm.nvvm.rcp.rm.d(double)
-declare double @llvm.nvvm.rcp.rn.d(double)
-declare float @llvm.nvvm.rcp.rn.f(float)
-declare float @llvm.nvvm.rcp.rn.ftz.f(float)
-declare double @llvm.nvvm.round.d(double)
-declare float @llvm.nvvm.round.f(float)
-declare float @llvm.nvvm.round.ftz.f(float)
-declare float @llvm.nvvm.sqrt.f(float)
-declare double @llvm.nvvm.sqrt.rn.d(double)
-declare float @llvm.nvvm.sqrt.rn.f(float)
-declare float @llvm.nvvm.sqrt.rn.ftz.f(float)
-declare double @llvm.nvvm.trunc.d(double)
-declare float @llvm.nvvm.trunc.f(float)
-declare float @llvm.nvvm.trunc.ftz.f(float)
-declare double @llvm.nvvm.ui2d.rz(i32)
-declare float @llvm.nvvm.ui2f.rn(i32)
-declare float @llvm.nvvm.ui2f.rz(i32)
-declare double @llvm.nvvm.ull2d.rz(i64)
-declare float @llvm.nvvm.ull2f.rz(i64)
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