[PATCH] D33294: Only enable LiveRangeShrink for x86.

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL303292: Only enable LiveRangeShrink for x86. (authored by dehao).

Changed prior to commit:
  https://reviews.llvm.org/D33294?vs=99334&id=99341#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D33294

Files:
  llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
  llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
  llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll
  llvm/trunk/test/CodeGen/NVPTX/sched1.ll
  llvm/trunk/test/CodeGen/NVPTX/sched2.ll
  llvm/trunk/test/CodeGen/SPARC/LeonItinerariesUT.ll


Index: llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
+++ llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
@@ -623,9 +623,6 @@
     addPass(&LocalStackSlotAllocationID, false);
   }
 
-  if (getOptLevel() != CodeGenOpt::None)
-    addPass(&LiveRangeShrinkID);
-
   // Run pre-ra passes.
   addPreRegAlloc();
 
Index: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
@@ -438,6 +438,7 @@
 
 void X86PassConfig::addPreRegAlloc() {
   if (getOptLevel() != CodeGenOpt::None) {
+    addPass(&LiveRangeShrinkID);
     addPass(createX86FixupSetCC());
     addPass(createX86OptimizeLEAs());
     addPass(createX86CallFrameOptimization());
Index: llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll
+++ llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll
@@ -378,11 +378,11 @@
 ; CHECK-NEXT: cmp x0, #13
 ; CHECK-NOT: ccmp
 ; CHECK-NEXT: cset [[REG1:w[0-9]+]], gt
-; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]
 ; CHECK-NEXT: cmp x2, #2
 ; CHECK-NEXT: cset [[REG2:w[0-9]+]], lt
 ; CHECK-NEXT: cmp x2, #4
 ; CHECK-NEXT: cset [[REG3:w[0-9]+]], gt
+; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]
 ; CHECK-NEXT: and [[REG5:w[0-9]+]], [[REG2]], [[REG3]]
 ; CHECK-NEXT: orr [[REG6:w[0-9]+]], [[REG4]], [[REG5]]
 ; CHECK-NEXT: cmp [[REG6]], #0
Index: llvm/trunk/test/CodeGen/NVPTX/sched2.ll
===================================================================
--- llvm/trunk/test/CodeGen/NVPTX/sched2.ll
+++ llvm/trunk/test/CodeGen/NVPTX/sched2.ll
@@ -4,12 +4,12 @@
 ; CHECK: .func foo
 ; CHECK: ld.v2.u32
 ; CHECK-NEXT: ld.v2.u32
+; CHECK-NEXT: ld.v2.u32
+; CHECK-NEXT: ld.v2.u32
 ; CHECK-NEXT: add.s32
 ; CHECK-NEXT: add.s32
-; CHECK-NEXT: ld.v2.u32
 ; CHECK-NEXT: add.s32
 ; CHECK-NEXT: add.s32
-; CHECK-NEXT: ld.v2.u32
 ; CHECK-NEXT: add.s32
 ; CHECK-NEXT: add.s32
   %ptr0 = getelementptr <2 x i32>, <2 x i32>* %a, i32 0
Index: llvm/trunk/test/CodeGen/NVPTX/sched1.ll
===================================================================
--- llvm/trunk/test/CodeGen/NVPTX/sched1.ll
+++ llvm/trunk/test/CodeGen/NVPTX/sched1.ll
@@ -6,11 +6,11 @@
 ; CHECK: .func foo
 ; CHECK: ld.u32
 ; CHECK-NEXT: ld.u32
-; CHECK-NEXT: add.s32
 ; CHECK-NEXT: ld.u32
-; CHECK-NEXT: add.s32
 ; CHECK-NEXT: ld.u32
 ; CHECK-NEXT: add.s32
+; CHECK-NEXT: add.s32
+; CHECK-NEXT: add.s32
   %ptr0 = getelementptr i32, i32* %a, i32 0
   %val0 = load i32, i32* %ptr0
   %ptr1 = getelementptr i32, i32* %a, i32 1
Index: llvm/trunk/test/CodeGen/SPARC/LeonItinerariesUT.ll
===================================================================
--- llvm/trunk/test/CodeGen/SPARC/LeonItinerariesUT.ll
+++ llvm/trunk/test/CodeGen/SPARC/LeonItinerariesUT.ll
@@ -28,8 +28,8 @@
 ; LEON3_4_ITIN-LABEL: f32_ops:
 ; LEON3_4_ITIN:       ld 
 ; LEON3_4_ITIN-NEXT:  ld 
-; LEON3_4_ITIN-NEXT:  fadds 
 ; LEON3_4_ITIN-NEXT:  ld 
+; LEON3_4_ITIN-NEXT:  fadds 
 ; LEON3_4_ITIN-NEXT:  ld 
 ; LEON3_4_ITIN-NEXT:  fsubs 
 ; LEON3_4_ITIN-NEXT:  fmuls 


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