[PATCH] D28152: Cortex-A57 scheduling model for ARM backend (AArch32)

[Andrew Zhogin via Phabricator via llvm-commits]

andrew.zhogin marked 3 inline comments as done.
andrew.zhogin added inline comments.


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Comment at: lib/Target/ARM/ARMScheduleA57.td:263
+// latency from documentration: 4 ­‐ 20, maximum taken
+def : InstRW<[A57Write_20cyc_1M], (instregex "(t2)?SDIV", "(t2)?UDIV")>;
+
----------------
javed.absar wrote:
> andrew.zhogin wrote:
> > javed.absar wrote:
> > > Would it be possible to Alias some of these to Sched classes that are pre-defined in ARMSchedule.td e.g. SchedAlias A57Write_20cyc_1M to WriteMUL/WriteDIV. That way the model could be more compact.
> > I don't think it is a good idea. For example, SDIV/UDIV instructions are not binded to WriteDIV SchedWrite. They are binded to IIC_iDIV InstrItinClass (as I see in ARMInstrInfo.td).
> > That's why I prefer to have full target-specific model binded only to instruction names.
> > Am I missing something?
> They are bound to both IIC_iDIV and " Sched<[WriteDIV]>;"  Please see last item in the list: 
> 
> def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
>                    "sdiv", "\t$Rd, $Rn, $Rm",
>                    [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
>            Requires<[IsARM, HasDivideInARM]>,
> Sched<[WriteDIV]>;
Yes, I have updated code to the current repository state and implemented aliases.
Do you think this patch is ok now?


https://reviews.llvm.org/D28152