[llvm] r303174 - [LV] Avoid potentential division by zero when selecting IC

[Matthew Simpson via llvm-commits]

Author: mssimpso
Date: Tue May 16 09:43:55 2017
New Revision: 303174

URL: http://llvm.org/viewvc/llvm-project?rev=303174&view=rev
Log:
[LV] Avoid potentential division by zero when selecting IC

Added:
    llvm/trunk/test/Transforms/LoopVectorize/interleave_count.ll
Modified:
    llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp

Modified: llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp?rev=303174&r1=303173&r2=303174&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp (original)
+++ llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp Tue May 16 09:43:55 2017
@@ -6550,8 +6550,8 @@ unsigned LoopVectorizationCostModel::sel
     // We assume that the cost overhead is 1 and we use the cost model
     // to estimate the cost of the loop and interleave until the cost of the
     // loop overhead is about 5% of the cost of the loop.
-    unsigned SmallIC =
-        std::min(IC, (unsigned)PowerOf2Floor(SmallLoopCost / LoopCost));
+    unsigned SmallIC = std::min(
+        IC, (unsigned)PowerOf2Floor(SmallLoopCost / LoopCost ? LoopCost : 1));
 
     // Interleave until store/load ports (estimated by max interleave count) are
     // saturated.

Added: llvm/trunk/test/Transforms/LoopVectorize/interleave_count.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/interleave_count.ll?rev=303174&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopVectorize/interleave_count.ll (added)
+++ llvm/trunk/test/Transforms/LoopVectorize/interleave_count.ll Tue May 16 09:43:55 2017
@@ -0,0 +1,33 @@
+; RUN: opt < %s -loop-vectorize -force-target-instruction-cost=0 -force-vector-width=2 -instcombine -S | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+
+; CHECK-LABEL: @copy(
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ]
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i64, i64* %a, i64 [[INDEX]]
+; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i64, i64* %b, i64 [[INDEX]]
+; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i64* [[TMP3]] to <2 x i64>*
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <2 x i64>, <2 x i64>* [[TMP4]], align 8
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i64* [[TMP2]] to <2 x i64>*
+; CHECK-NEXT:    store <2 x i64> [[WIDE_LOAD]], <2 x i64>* [[TMP5]], align 8
+; CHECK-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 2
+; CHECK:         br i1 {{.*}}, label %middle.block, label %vector.body
+;
+define void @copy(i64* %a, i64* %b, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
+  %tmp0 = getelementptr inbounds i64, i64* %a, i64 %i
+  %tmp1 = getelementptr inbounds i64, i64* %b, i64 %i
+  %tmp3 = load i64, i64* %tmp1, align 8
+  store i64 %tmp3, i64* %tmp0, align 8
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp slt i64 %i.next, %n
+  br i1 %cond, label %for.body, label %for.end
+
+for.end:
+  ret void
+}