[llvm] r303137 - AMDGPUCodeGen: Fix warnings in r303111. [-Wunused-variable]

[NAKAMURA Takumi via llvm-commits]

Author: chapuni
Date: Mon May 15 23:01:23 2017
New Revision: 303137

URL: http://llvm.org/viewvc/llvm-project?rev=303137&view=rev
Log:
AMDGPUCodeGen: Fix warnings in r303111. [-Wunused-variable]

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp?rev=303137&r1=303136&r2=303137&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp Mon May 15 23:01:23 2017
@@ -136,9 +136,11 @@ void PHILinearize::phiInfoElementAddSour
   // sources, because we cannot have different registers with
   // identical predecessors, but we can have the same register for
   // multiple predecessors.
+#if !defined(NDEBUG)
   for (auto SI : phiInfoElementGetSources(Info)) {
     assert((SI.second != SourceMBB || SourceReg == SI.first));
   }
+#endif
 
   phiInfoElementGetSources(Info).insert(PHISourceT(SourceReg, SourceMBB));
 }

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=303137&r1=303136&r2=303137&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Mon May 15 23:01:23 2017
@@ -564,8 +564,8 @@ void SIInstrInfo::insertVectorSelect(Mac
                                      unsigned TrueReg,
                                      unsigned FalseReg) const {
   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
-  const TargetRegisterClass *RegClass = MRI.getRegClass(DstReg);
-  assert(RegClass == &AMDGPU::VGPR_32RegClass && "Not a VGPR32 reg");
+  assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
+         "Not a VGPR32 reg");
 
   if (Cond.size() == 1) {
     BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)