[PATCH] D33169: [X86] Adding vpopcntd and vpopcntq instructions

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

A possible addition would be to custom lower i8/i16 vectors with a trunc(popcnt(zext))) pattern.

> In https://reviews.llvm.org/D33169#754377, @RKSimon wrote:
> 
>> Disassembler tests?
> 
> 
> I believe that the test test/MC/X86/x86-64-avx512vpopcntdq.s covers the required tests. 
>  If you think additional tests are required i will appreciate an example.

I don't think the MC tests actually use the disassembler code to try and get back to the instruction - @craig.topper can you confirm?

> In https://reviews.llvm.org/D33169#754316, @RKSimon wrote:
> 
>> Add cost-model support in X86TTIImpl::getIntrinsicInstrCost
> 
> 
> Since AVX512 is missing from the cost table and since i need some investigation on this subject, I prefer to make this changes in different patch.

OK.



================
Comment at: lib/Target/X86/X86InstrInfo.cpp:7042
+  case X86::VPOPCNTDZrr:   case X86::VPOPCNTDZrm:
+  case X86::VPOPCNTQZrr:   case X86::VPOPCNTQZrm:
   case X86::TZCNT16rr: case X86::TZCNT16rm:
----------------
craig.topper wrote:
> I think this also an EFLAGS related piece of code. So the vector pop br shouldn't be here.
+1 - I don't think this is going to work for vectors, but you can try later if you want.


================
Comment at: test/CodeGen/X86/avx512vpopcntdq-intrinsics.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512vpopcntdq | FileCheck %s
+
----------------
Add  --show-mc-encoding ?


Repository:
  rL LLVM

https://reviews.llvm.org/D33169