[PATCH] D33196: [AArch64] Explicitly enable FeatureFuseLiterals on Cortex-A72 (NFC).

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
Herald added subscribers: javed.absar, aemerson.

This feature explicitly enables the fusion of instructions for literal
generation and PC-relative address calculations on Cortex-A72, as
recommended in its Software Optimisation Guide, sections 4.11 and
4.12. This is a NFC, as the Cortex-A72 currently uses the Cortex-A57
processor model which already schedules those instructions back-to-back
when the PostRAScheduler is not used.


https://reviews.llvm.org/D33196

Files:
  lib/Target/AArch64/AArch64.td
  test/CodeGen/AArch64/misched-fusion-lit.ll


Index: test/CodeGen/AArch64/misched-fusion-lit.ll
===================================================================
--- test/CodeGen/AArch64/misched-fusion-lit.ll
+++ test/CodeGen/AArch64/misched-fusion-lit.ll
@@ -1,6 +1,7 @@
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=-fuse-literals | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKDONT
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-literals | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57      | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72      | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
 
 @g = common local_unnamed_addr global i8* null, align 8
 
Index: lib/Target/AArch64/AArch64.td
===================================================================
--- lib/Target/AArch64/AArch64.td
+++ lib/Target/AArch64/AArch64.td
@@ -217,6 +217,7 @@
                                    FeatureCrypto,
                                    FeatureFPARMv8,
                                    FeatureNEON,
+                                   FeatureFuseLiterals,
                                    FeaturePerfMon
                                    ]>;
 


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