[PATCH] D31851: [PowerPC] Eliminate compares - add handling for logical operations without the use of condition registers

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai updated this revision to Diff 98986.
nemanjai added a comment.

This is a significantly scoped-down version of this patch to make it more manageable for review. It simply extends the use of the existing handling of ISD::SETCC in GPRs to their uses in logic operations (AND/OR/XOR).

Furthermore, this adds a restriction to the SETCC handling to only perform the expansion if all the uses need the value in a GPR since doing the expansion in such a situation would be a net addition of instructions without being able to eliminate the compare instruction.


Repository:
  rL LLVM

https://reviews.llvm.org/D31851

Files:
  lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  test/CodeGen/PowerPC/logic-ops-on-compares.ll

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