[PATCH] D18738: Add new !unconditionally_dereferenceable load instruction metadata

[Sanjoy Das via Phabricator via llvm-commits]

sanjoy added a comment.

In https://reviews.llvm.org/D18738#752215, @whitequark wrote:

> @sanjoy Since https://reviews.llvm.org/D20116 is in, is there any reason to avoid having a `!speculatable` on load instructions? It can be emulated anyway by defining a class of `@load.x` functions marked speculatable and their return value dereferenceable, so there is no loss of soundness.


I'd be okay (even happy! :) ) if you add a `@llvm.safe.load.<ty>` intrinsic that never has UB, and returns `undef` if the address passed to it is not dereferenceable.  That intrinsic could then be marked `speculatable`.  If needed, we could even //implement// the intrinsic by trying to read from the address passed in, and by catching the `SIGSEGV` or `SIGBUS`, if any.

However, I don't think we agreed allowing a per-site `speculatable` attribute, which is analogous to what you're suggesting IIUC -- a per-load `!speculatable` tag.


Repository:
  rL LLVM

https://reviews.llvm.org/D18738