[PATCH] D33076: [PPC] Move the combine "a << (b % (sizeof(a) * 8)) -> (PPCshl a, b)" to the backend. NFC.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Looks fine, but someone who knows PPC better should approve.



================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:122
+      /// amounts are supported - the actual bits shifted is the modulo result
+      /// of the amount and the element width.
       SRL, SRA, SHL,
----------------
Maybe leave the comment noting that 32-bit shifts are modulo 64?


https://reviews.llvm.org/D33076