[PATCH] D32916: [DAGCombine] (addcarry 0, 0, X) -> (ext/trunc X)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In https://reviews.llvm.org/D32916#749759, @spatel wrote:

> See inline for a few nits, but I think this makes sense now. If I'm seeing the diffs correctly, there was no codegen difference for x86 after adding the 'and' mask, so we must be recognizing and optimizing that pattern. @RKSimon - do you see any other problems?


This looks right to me now - thanks for reviewing the getBoolExtOrTrunc usage.

Other than what's to be done with the mul-i1024 this looks good to go.



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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2151
+    SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT);
+    AddToWorklist(CarryExt.getNode());
+    return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt,
----------------
spatel wrote:
> Do you need to explicitly add to worklist? I thought this gets handled automatically by the combiner.
Yes, this should be kept.


https://reviews.llvm.org/D32916