[PATCH] D32201: [RALLOC] Increase CSR cost in RegAllocGreedy to favour splitting over CSR first use

[Wei Mi via llvm-commits]

Ping.

On Tue, Apr 18, 2017 at 5:02 PM, Wei Mi via Phabricator
<reviews at reviews.llvm.org> wrote:
> wmi created this revision.
> Herald added a reviewer: javed.absar.
>
> The patch is to solve the problem mentioned in PR29154. It is evolved from https://reviews.llvm.org/D27366.
>
> The patch raises the CSR cost to be 1/4 of the func entry frequency, so that live range will use CSR only when its splitting cost or spill cost is close to or higher than the func entry frequency, otherwise regalloc will choose to split or spill the live range. After the split or spill, live ranges allocated to CSR registers will be shortened and will only be used in cold places, so that we may get better chances to do shrinkwrapping. Another potential benefit is that param passing copy may be sinked from entry to a colder branch.
>
> Internal testing shows it improves several benchmarks, such as zippy (+0.8%), protobuf (+1.9%) and some other microbenchmarks without specified names.
>
>
> Repository:
>   rL LLVM
>
> https://reviews.llvm.org/D32201
>
> Files:
>   lib/CodeGen/RegAllocGreedy.cpp
>   lib/Target/AArch64/AArch64RegisterInfo.h
>   lib/Target/ARM/ARMBaseRegisterInfo.h
>   lib/Target/PowerPC/PPCRegisterInfo.h
>   lib/Target/X86/X86RegisterInfo.h
>   test/CodeGen/ARM/divmod-eabi.ll
>   test/CodeGen/X86/atom-fixup-lea2.ll
>   test/CodeGen/X86/block-placement.ll
>   test/CodeGen/X86/csr-split1.ll
>   test/CodeGen/X86/mul-i1024.ll
>   test/CodeGen/X86/mul-i512.ll
>   test/CodeGen/X86/ragreedy-bug.ll
>   test/CodeGen/X86/ragreedy-hoist-spill.ll
>   test/CodeGen/X86/sjlj-eh.ll
>   test/CodeGen/X86/x86-shrink-wrapping.ll
>   test/DebugInfo/X86/live-debug-values.ll
>