[llvm] r301955 - [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCREL
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Tue May 2 11:15:34 PDT 2017
Author: kparzysz
Date: Tue May 2 13:15:33 2017
New Revision: 301955
URL: http://llvm.org/viewvc/llvm-project?rev=301955&view=rev
Log:
[Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCREL
Patch by Sid Manning.
Added:
llvm/trunk/test/CodeGen/Hexagon/plt-rel.ll
llvm/trunk/test/MC/Hexagon/plt-rel.s
Modified:
llvm/trunk/include/llvm/Support/ELFRelocs/Hexagon.def
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
Modified: llvm/trunk/include/llvm/Support/ELFRelocs/Hexagon.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELFRelocs/Hexagon.def?rev=301955&r1=301954&r2=301955&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ELFRelocs/Hexagon.def (original)
+++ llvm/trunk/include/llvm/Support/ELFRelocs/Hexagon.def Tue May 2 13:15:33 2017
@@ -99,3 +99,7 @@ ELF_RELOC(R_HEX_LD_GOT_32_6_X, 91)
ELF_RELOC(R_HEX_LD_GOT_16_X, 92)
ELF_RELOC(R_HEX_LD_GOT_11_X, 93)
ELF_RELOC(R_HEX_23_REG, 94)
+ELF_RELOC(R_HEX_GD_PLT_B22_PCREL_X, 95)
+ELF_RELOC(R_HEX_GD_PLT_B32_PCREL_X, 96)
+ELF_RELOC(R_HEX_LD_PLT_B22_PCREL_X, 97)
+ELF_RELOC(R_HEX_LD_PLT_B32_PCREL_X, 98)
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=301955&r1=301954&r2=301955&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Tue May 2 13:15:33 2017
@@ -1720,8 +1720,13 @@ HexagonTargetLowering::LowerToTLSGeneral
Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
InFlag = Chain.getValue(1);
+ unsigned Flags =
+ static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
+ ? HexagonII::MO_GDPLT | HexagonII::HMOTF_ConstExtended
+ : HexagonII::MO_GDPLT;
+
return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
- Hexagon::R0, HexagonII::MO_GDPLT);
+ Hexagon::R0, Flags);
}
//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp?rev=301955&r1=301954&r2=301955&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp Tue May 2 13:15:33 2017
@@ -39,7 +39,7 @@ static MCOperand GetSymbolRef(const Mach
// Populate the relocation type based on Hexagon target flags
// set on an operand
MCSymbolRefExpr::VariantKind RelocationType;
- switch (MO.getTargetFlags()) {
+ switch (MO.getTargetFlags() & ~HexagonII::HMOTF_ConstExtended) {
default:
RelocationType = MCSymbolRefExpr::VK_None;
break;
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=301955&r1=301954&r2=301955&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp Tue May 2 13:15:33 2017
@@ -184,7 +184,11 @@ public:
{ "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },
{ "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
{ "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
- { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 }
+ { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 },
+ { "fixup_Hexagon_GD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_GD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_LD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_LD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }
};
if (Kind < FirstTargetFixupKind)
@@ -291,6 +295,10 @@ public:
case fixup_Hexagon_32_PCREL:
case fixup_Hexagon_6_PCREL_X:
case fixup_Hexagon_23_REG:
+ case fixup_Hexagon_GD_PLT_B22_PCREL_X:
+ case fixup_Hexagon_GD_PLT_B32_PCREL_X:
+ case fixup_Hexagon_LD_PLT_B22_PCREL_X:
+ case fixup_Hexagon_LD_PLT_B32_PCREL_X:
// These relocations should always have a relocation recorded
IsResolved = false;
return;
@@ -347,6 +355,8 @@ public:
case fixup_Hexagon_B9_PCREL_X:
case fixup_Hexagon_B7_PCREL:
case fixup_Hexagon_B7_PCREL_X:
+ case fixup_Hexagon_GD_PLT_B32_PCREL_X:
+ case fixup_Hexagon_LD_PLT_B32_PCREL_X:
return 4;
}
}
@@ -374,6 +384,8 @@ public:
break;
case fixup_Hexagon_B32_PCREL_X:
+ case fixup_Hexagon_GD_PLT_B32_PCREL_X:
+ case fixup_Hexagon_LD_PLT_B32_PCREL_X:
Value >>= 6;
break;
}
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp?rev=301955&r1=301954&r2=301955&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp Tue May 2 13:15:33 2017
@@ -284,6 +284,14 @@ unsigned HexagonELFObjectWriter::getRelo
return ELF::R_HEX_TPREL_11_X;
case fixup_Hexagon_23_REG:
return ELF::R_HEX_23_REG;
+ case fixup_Hexagon_GD_PLT_B22_PCREL_X:
+ return ELF::R_HEX_GD_PLT_B22_PCREL_X;
+ case fixup_Hexagon_GD_PLT_B32_PCREL_X:
+ return ELF::R_HEX_GD_PLT_B32_PCREL_X;
+ case fixup_Hexagon_LD_PLT_B22_PCREL_X:
+ return ELF::R_HEX_LD_PLT_B22_PCREL_X;
+ case fixup_Hexagon_LD_PLT_B32_PCREL_X:
+ return ELF::R_HEX_LD_PLT_B32_PCREL_X;
}
}
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h?rev=301955&r1=301954&r2=301955&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h Tue May 2 13:15:33 2017
@@ -111,6 +111,10 @@ enum Fixups {
fixup_Hexagon_TPREL_16_X,
fixup_Hexagon_TPREL_11_X,
fixup_Hexagon_23_REG,
+ fixup_Hexagon_GD_PLT_B22_PCREL_X,
+ fixup_Hexagon_GD_PLT_B32_PCREL_X,
+ fixup_Hexagon_LD_PLT_B22_PCREL_X,
+ fixup_Hexagon_LD_PLT_B32_PCREL_X,
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp?rev=301955&r1=301954&r2=301955&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp Tue May 2 13:15:33 2017
@@ -199,6 +199,11 @@ Hexagon::Fixups HexagonMCCodeEmitter::ge
return Hexagon::fixup_Hexagon_IE_GOT_32_6_X;
case MCSymbolRefExpr::VK_Hexagon_PCREL:
return Hexagon::fixup_Hexagon_B32_PCREL_X;
+ case MCSymbolRefExpr::VK_Hexagon_GD_PLT:
+ return Hexagon::fixup_Hexagon_GD_PLT_B32_PCREL_X;
+ case MCSymbolRefExpr::VK_Hexagon_LD_PLT:
+ return Hexagon::fixup_Hexagon_LD_PLT_B32_PCREL_X;
+
case MCSymbolRefExpr::VK_None: {
auto Insts = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
for (auto I = Insts.begin(), N = Insts.end(); I != N; ++I) {
@@ -318,6 +323,8 @@ namespace {
case fixup_Hexagon_PLT_B22_PCREL:
case fixup_Hexagon_GD_PLT_B22_PCREL:
case fixup_Hexagon_LD_PLT_B22_PCREL:
+ case fixup_Hexagon_GD_PLT_B22_PCREL_X:
+ case fixup_Hexagon_LD_PLT_B22_PCREL_X:
case fixup_Hexagon_6_PCREL_X:
return true;
default:
@@ -414,10 +421,12 @@ unsigned HexagonMCCodeEmitter::getExprOp
case 22:
switch (kind) {
case MCSymbolRefExpr::VK_Hexagon_GD_PLT:
- FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL;
+ FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X
+ : Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL;
break;
case MCSymbolRefExpr::VK_Hexagon_LD_PLT:
- FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL;
+ FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X
+ : Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL;
break;
case MCSymbolRefExpr::VK_None:
FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
@@ -593,6 +602,12 @@ unsigned HexagonMCCodeEmitter::getExprOp
case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X;
break;
+ case MCSymbolRefExpr::VK_Hexagon_GD_PLT:
+ FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X;
+ break;
+ case MCSymbolRefExpr::VK_Hexagon_LD_PLT:
+ FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X;
+ break;
case MCSymbolRefExpr::VK_None:
FixupKind = Hexagon::fixup_Hexagon_11_X;
break;
Added: llvm/trunk/test/CodeGen/Hexagon/plt-rel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/plt-rel.ll?rev=301955&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/plt-rel.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/plt-rel.ll Tue May 2 13:15:33 2017
@@ -0,0 +1,37 @@
+; RUN: llc -march=hexagon -relocation-model=pic -mattr=+long-calls < %s | FileCheck --check-prefix=CHECK-LONG %s
+; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s
+
+; CHECK-LONG: call ##_ZL13g_usr1_called at GDPLT
+; CHECK-LONG-NOT: call _ZL13g_usr1_called at GDPLT
+; CHECK: call _ZL13g_usr1_called at GDPLT
+; CHECK-NOT: call ##_ZL13g_usr1_called at GDPLT
+
+
+target triple = "hexagon"
+
+ at _ZL13g_usr1_called = internal thread_local global i32 0, align 4
+
+; Function Attrs: norecurse nounwind
+define void @_Z14SigUsr1Handleri(i32) local_unnamed_addr #0 {
+entry:
+ store volatile i32 1, i32* @_ZL13g_usr1_called, align 4
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define zeroext i1 @_Z27CheckForMonitorCancellationv() local_unnamed_addr #0 {
+entry:
+ %0 = load volatile i32, i32* @_ZL13g_usr1_called, align 4
+ %tobool = icmp eq i32 %0, 0
+ br i1 %tobool, label %return, label %if.then
+
+if.then: ; preds = %entry
+ store volatile i32 0, i32* @_ZL13g_usr1_called, align 4
+ br label %return
+
+return: ; preds = %entry, %if.then
+ %.sink = phi i1 [ true, %if.then ], [ false, %entry ]
+ ret i1 %.sink
+}
+
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
Added: llvm/trunk/test/MC/Hexagon/plt-rel.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/plt-rel.s?rev=301955&view=auto
==============================================================================
--- llvm/trunk/test/MC/Hexagon/plt-rel.s (added)
+++ llvm/trunk/test/MC/Hexagon/plt-rel.s Tue May 2 13:15:33 2017
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d -r - | FileCheck %s
+
+call foo at GDPLT
+# CHECK: R_HEX_GD_PLT_B22_PCREL
+call ##foo at GDPLT
+# CHECK: R_HEX_GD_PLT_B32_PCREL_X
+# CHECK-NEXT: R_HEX_GD_PLT_B22_PCREL_X
+
+call foo at LDPLT
+# CHECK: R_HEX_LD_PLT_B22_PCREL
+call ##foo at LDPLT
+# CHECK: R_HEX_LD_PLT_B32_PCREL_X
+# CHECK-NEXT: R_HEX_LD_PLT_B22_PCREL_X
More information about the llvm-commits
mailing list