[PATCH] D32755: [DAGCombine] (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix created this revision.

Do the transform when the carry isn't used. It's a pattern exposed when legalizing large integers.


https://reviews.llvm.org/D32755

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/addcarry.ll


Index: test/CodeGen/X86/addcarry.ll
===================================================================
--- test/CodeGen/X86/addcarry.ll
+++ test/CodeGen/X86/addcarry.ll
@@ -190,9 +190,9 @@
 define i64 @shiftadd(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: shiftadd:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    leaq (%rdx,%rcx), %rax
 ; CHECK-NEXT:    addq %rsi, %rdi
-; CHECK-NEXT:    adcq $0, %rax
+; CHECK-NEXT:    adcq %rcx, %rdx
+; CHECK-NEXT:    movq %rdx, %rax
 ; CHECK-NEXT:    retq
 entry:
   %0 = zext i64 %a to i128
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -242,6 +242,7 @@
     SDValue visitUSUBO(SDNode *N);
     SDValue visitADDE(SDNode *N);
     SDValue visitADDCARRY(SDNode *N);
+    SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
     SDValue visitSUBE(SDNode *N);
     SDValue visitSUBCARRY(SDNode *N);
     SDValue visitMUL(SDNode *N);
@@ -2142,6 +2143,26 @@
   if (isNullConstant(CarryIn))
     return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(), N0, N1);
 
+  if (SDValue Combined = visitADDCARRYLike(N0, N1, CarryIn, N))
+    return Combined;
+
+  if (SDValue Combined = visitADDCARRYLike(N1, N0, CarryIn, N))
+    return Combined;
+
+  return SDValue();
+}
+
+SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
+                                       SDNode *N) {
+  // If the flag result is dead, we can do transform that invalidate it.
+  if (!N->hasAnyUseOfValue(1)) {
+    // (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
+    if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::UADDO) &&
+        isNullConstant(N1))
+      return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
+                         N0.getOperand(0), N0.getOperand(1), CarryIn);
+  }
+
   return SDValue();
 }
 


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