[PATCH] D28152: Cortex-A57 scheduling model for ARM backend (AArch32)

[Andrew Zhogin via Phabricator via llvm-commits]

andrew.zhogin added inline comments.


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Comment at: lib/Target/ARM/ARMScheduleA57.td:263
+// latency from documentration: 4 ­‐ 20, maximum taken
+def : InstRW<[A57Write_20cyc_1M], (instregex "(t2)?SDIV", "(t2)?UDIV")>;
+
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javed.absar wrote:
> Would it be possible to Alias some of these to Sched classes that are pre-defined in ARMSchedule.td e.g. SchedAlias A57Write_20cyc_1M to WriteMUL/WriteDIV. That way the model could be more compact.
I don't think it is a good idea. For example, SDIV/UDIV instructions are not binded to WriteDIV SchedWrite. They are binded to IIC_iDIV InstrItinClass (as I see in ARMInstrInfo.td).
That's why I prefer to have full target-specific model binded only to instruction names.
Am I missing something?


https://reviews.llvm.org/D28152