[PATCH] D32533: [SLPVectorizer] Limit the number of block chain instructions to max register size

[Anna Thomas via Phabricator via llvm-commits]

anna added a subscriber: mssimpso.
anna added a comment.

Hi Max, 
I think we are allowed to have vector operations (other than vector stores) on vector sizes greater than `getMaxVecRegSize` in the IR. In the SLP vectorizer, we look for the max size when storing. Both GEP vectorization and phi-vectorization goes by the number of scalar elements chosen for vectorization, rather than the `R.getMaxVecRegSize` (for example, GEP chooses chunks of 16).  Also, looking at all the llvm tests, there are many cases where geps, shuffles, inserts and extracts operate on <16 x i64> vector types = 1024 bits. The maxVecRegSize among all targets is 512 bits (zmm registers in AVX512). Running this through codegen, I can see we use the correct vector register size allowed at the target, even though the IR has <16 x i64>. Given this, I don't think this is a bug.

@mssimpso Is this correct? Also, I would like to know the design philosophy behind having the large vector sizes, and allowing LLC to find the correct vector register size.


https://reviews.llvm.org/D32533