[PATCH] D30086: Add generic IR vector reductions

[Amara Emerson via Phabricator via llvm-commits]

aemerson marked 2 inline comments as done.
aemerson added a comment.

At the moment nothing is emitting strict float reductions as no target supports it. We have it implemented for SVE but the IR type and vectorizer changes aren't upstream yet. The reason I've had to include it in this patch is because we want to agree on an intrinsics spec first without changing it later when SVE support lands.



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Comment at: include/llvm/CodeGen/SelectionDAGNodes.h:1077
+  }
+};
+
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RKSimon wrote:
> If possible I'd like to see this generalization of the SDNodeFlags support added separately first, reducing this patch and allow us to get on with adding triple node support for FMA opcodes.
I can do that. There's a dependency on the new opcodes for the isUnaryOpWithFlags function but I'll leave that blank returning false in the generalisation patch and add the opcodes in this patch.


Repository:
  rL LLVM

https://reviews.llvm.org/D30086