[PATCH] D31944: [DAGCombiner] add (sext i1 X), 1 --> zext (not i1 X)

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 96580.
spatel added a comment.

Patch updated:
Added more vector tests and rebased test diffs after:
https://reviews.llvm.org/rL300725
https://reviews.llvm.org/rL300763
https://reviews.llvm.org/rL300772

I made changes to the DAG's simplifyDemandedBits and then got distracted with related IR transforms...
The demanded-bits changes helped x86 vector codegen in the way I expected, but I think the ARM regressions show that we're missing some generic folds.

Let me know if there are other tests we should have to expose these folds.


https://reviews.llvm.org/D31944

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/ARM/bool-ext-inc.ll
  test/CodeGen/X86/bool-ext-inc.ll

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