[PATCH] D32219: [X86][SSE] Improve DIV/SQRT throughput estimates for SB/HW schedule models

[Gadi Haber via Phabricator via llvm-commits]

gadi.haber added inline comments.


================
Comment at: lib/Target/X86/X86SchedHaswell.td:139
 
+def : WriteRes<WriteFDiv, [HWPort0]> {
+  let Latency = 12; // 10-14 cycles.
----------------
let NumMicroOps = 1;



================
Comment at: lib/Target/X86/X86SchedHaswell.td:143
+}
+def : WriteRes<WriteFDivLd, [HWPort23, HWPort0]> {
+  let Latency = 16; // load + 10-14 cycles.
----------------
let NumMicroOps = 2;


================
Comment at: lib/Target/X86/X86SchedHaswell.td:148
+
+def : WriteRes<WriteFSqrt, [HWPort0]> {
+  let Latency = 15;
----------------
let NumMicroOps = 1;


================
Comment at: lib/Target/X86/X86SchedHaswell.td:152
+}
+def : WriteRes<WriteFSqrtLd, [HWPort23, HWPort0]> {
+  let Latency = 19;
----------------
let NumMicroOps = 2;


================
Comment at: lib/Target/X86/X86SchedSandyBridge.td:126
+
+def : WriteRes<WriteFDiv, [SBPort0]> {
+  let Latency = 12; // 10-14 cycles.
----------------
let NumMicroOps = 1;


================
Comment at: lib/Target/X86/X86SchedSandyBridge.td:130
+}
+def : WriteRes<WriteFDivLd, [SBPort23, SBPort0]> {
+  let Latency = 16; // load + 10-14 cycles.
----------------
let NumMicroOps = 2;


================
Comment at: lib/Target/X86/X86SchedSandyBridge.td:135
+
+def : WriteRes<WriteFSqrt, [SBPort0]> {
+  let Latency = 15;
----------------
let NumMicroOps = 1;


================
Comment at: lib/Target/X86/X86SchedSandyBridge.td:139
+}
+def : WriteRes<WriteFSqrtLd, [SBPort23, SBPort0]> {
+  let Latency = 19;
----------------
let NumMicroOps = 2;


Repository:
  rL LLVM

https://reviews.llvm.org/D32219