[llvm] r300987 - [AArch64][Falkor] Refine modeling of store-release exclusive instructions.

Chad Rosier via llvm-commits llvm-commits at lists.llvm.org
Fri Apr 21 07:58:32 PDT 2017


Author: mcrosier
Date: Fri Apr 21 09:58:32 2017
New Revision: 300987

URL: http://llvm.org/viewvc/llvm-project?rev=300987&view=rev
Log:
[AArch64][Falkor] Refine modeling of store-release exclusive instructions.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td
    llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td?rev=300987&r1=300986&r2=300987&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td Fri Apr 21 09:58:32 2017
@@ -515,8 +515,8 @@ def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc]
 def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc], (instregex "^STXP(W|X)$")>;
 def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc], (instregex "^STXR(B|H|W|X)$")>;
 
-def : InstRW<[WriteSTX],              (instregex "^STLXP(W|X)$")>;
-def : InstRW<[WriteSTX],              (instregex "^STLXR(B|H|W|X)$")>;
+def : InstRW<[FalkorWr_2LD_1ST_1SD_3cyc], (instregex "^STLXP(W|X)$")>;
+def : InstRW<[FalkorWr_2LD_1ST_1SD_3cyc], (instregex "^STLXR(B|H|W|X)$")>;
 def : InstRW<[WriteVST, WriteVST],    (instrs STNPQi)>;
 
 // Store Instructions

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td?rev=300987&r1=300986&r2=300987&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td Fri Apr 21 09:58:32 2017
@@ -275,6 +275,12 @@ def FalkorWr_2LD_2none_3cyc: SchedWriteR
   let NumMicroOps = 4;
 }
 
+def FalkorWr_2LD_1ST_1SD_3cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitST,
+                                              FalkorUnitSD, FalkorUnitLD]> {
+  let Latency = 3;
+  let NumMicroOps = 4;
+}
+
 //===----------------------------------------------------------------------===//
 // Define 5 micro-op types
 




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