[PATCH] D32277: Replace slow LEA instructions in X86

[Lama via Phabricator via llvm-commits]

lsaba created this revision.

  According to Intel's Optimization Reference Manual for SNB+:
  " For LEA instructions with three source operands and some specific situations, instruction latency has increased to 3 cycles, and must
    dispatch via port 1:
  - LEA that has all three source operands: base, index, and offset
  - LEA that uses base and index registers where the base is EBP, RBP,or R13
  - LEA that uses RIP relative addressing mode
  - LEA that uses 16-bit addressing mode "

This patch currently handles the first 2 cases only.


https://reviews.llvm.org/D32277

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86FixupLEAs.cpp
  lib/Target/X86/X86TargetMachine.cpp
  test/CodeGen/X86/leaFixup32.mir
  test/CodeGen/X86/leaFixup64.mir

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