[PATCH] D32250: [Thumb-1] Fix corner cases for compressed jump tables

[Weiming Zhao via Phabricator via llvm-commits]

weimingz created this revision.
Herald added a subscriber: rengolin.

When synthesized TBB/TBH is expanded, we need to avoid:

1. the %base and %idx are the same register. E.g.: %https://reviews.llvm.org/diffusion/L/ = tLSLri %R2, 2 %R2 = tLEApcrelJT <jt#1> %https://reviews.llvm.org/diffusion/L/ = tLDRr %https://reviews.llvm.org/diffusion/L/, %R2 tBR_JTr %https://reviews.llvm.org/diffusion/L/ After JT comppression optimization, it becomes %R2 = tLEApcrelJT <jt#1> tTBH_JT %R2, %R2
2. BaseReg is redefined after the load of branching target. E.g.: 	%R2 = tLEApcrelJT <jt#1> %https://reviews.llvm.org/diffusion/L/ =  tLDRr %https://reviews.llvm.org/diffusion/L/, %R2

  	         %R2 = tLDRspi %SP, 12
  	         tBR_JTr %R1
          After JT compression, it becomes
                   %R2 = tLEApcrelJT <jt#1>
                   %R2 = tLDRspi %SP, 12
                   tTBB_JT %R2, %R1
                  
                   
       	
                         


https://reviews.llvm.org/D32250

Files:
  lib/Target/ARM/ARMConstantIslandPass.cpp


Index: lib/Target/ARM/ARMConstantIslandPass.cpp
===================================================================
--- lib/Target/ARM/ARMConstantIslandPass.cpp
+++ lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -2130,6 +2130,13 @@
       //   %idx = tLSLri %idx, 2
       //   %base = tLEApcrelJT
       //   %t = tLDRr %idx, %base
+      //
+      //   1) %base and %idx cannot be the same reg as during expansion, they
+      //      need to be in different registers.
+      //   2) %base cannot be redefined after %t. Otherwise, it becomes
+      //      %base =
+      //      %base =
+      //      tBB %base, %idx
       unsigned BaseReg = User.MI->getOperand(0).getReg();
 
       if (User.MI->getIterator() == User.MI->getParent()->begin())
@@ -2141,6 +2148,8 @@
         continue;
       IdxReg = Shift->getOperand(2).getReg();
       unsigned ShiftedIdxReg = Shift->getOperand(0).getReg();
+      if (BaseReg == IdxReg)
+        continue;
 
       // It's important that IdxReg is live until the actual TBB/TBH. Most of
       // the range is checked later, but the LEA might still clobber it and not
@@ -2158,6 +2167,12 @@
 
       // If we're in PIC mode, there should be another ADD following.
       auto *TRI = STI->getRegisterInfo();
+
+      // %base cannot be redefined after the load as it will appear before
+      // TBB/TBH.
+      if (registerDefinedBetween(BaseReg, Load->getNextNode(), MBB->end(), TRI))
+        continue;
+
       if (isPositionIndependentOrROPI) {
         MachineInstr *Add = Load->getNextNode();
         if (Add->getOpcode() != ARM::tADDrr ||


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