[PATCH] D24623: [AMDGPU] Implement memory model

[Tony Tye via Phabricator via llvm-commits]

t-tye added inline comments.


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Comment at: lib/Target/AMDGPU/SIMemoryLegalizer.cpp:361
+      ++MI;
+      Changed |= InsertWaitcntVmcnt0(MI);
+      Changed |= InsertBufferWbinvl1Vol(MI);
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Is this required if a DS memory operation? Seems it is only required if a VMEM or FLAT instruction to ensure it has completed before invalidating the cache.


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Comment at: lib/Target/AMDGPU/SIMemoryLegalizer.cpp:408
+      ++MI;
+      Changed |= InsertWaitcntVmcnt0(MI);
+      Changed |= InsertBufferWbinvl1Vol(MI);
----------------
Is this required if a DS memory operation? Seems it is only required if a VMEM or FLAT instruction to ensure it has completed before invalidating the cache.


https://reviews.llvm.org/D24623