[PATCH] D31944: [DAGCombiner] add (sext i1 X), 1 --> zext (not i1 X)

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In https://reviews.llvm.org/D31944#729560, @efriedma wrote:

> I'm not sure this is consistently beneficial; particularly for vectors, if the operand is a comparison (or something derived from a comparison), sign-extending it could be free.


Hmm...any ideas how to limit in that case? I was assuming that since we have:

  // select Cond, 0, 1 --> zext (!Cond)

...this also makes sense.

If we have a compare op, we should be able to fold the 'not' op introduced here directly into the compare predicate. Or in the case of a crippled ISA like SSE that lacks inverted predicates, we might be able to fold the 'not' into the zext/mask...but as I think we can see in the SSE test already included, we're missing that fold. Ie, instead of:

  movaps {{.*#+}} xmm1 = [1,1,1,1]
  xorps %xmm1, %xmm0
  andps %xmm1, %xmm0

We should have done:

  pandn	[1,1,1,1], %xmm0


https://reviews.llvm.org/D31944