[PATCH] D32028: [AArch64] Avoid partial register writes on lane 0 of BUILD_VECTOR for i8/i16/f16

[Adam Nemet via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL300276: [AArch64] Avoid partial register writes on lane 0 of BUILD_VECTOR for i8/i16/f16 (authored by anemet).

Changed prior to commit:
  https://reviews.llvm.org/D32028?vs=95153&id=95244#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D32028

Files:
  llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
  llvm/trunk/test/CodeGen/AArch64/arm64-neon-copy.ll
  llvm/trunk/test/CodeGen/AArch64/concat_vector-scalar-combine.ll

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