[PATCH] D31331: [mips][msa] Truncation of vector elements for instructions creating ISD::SHL, ISD::SRL or ISD::SRA nodes

[Simon Dardis via Phabricator via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

Testing this shows that test/CodeGen/Mips/msa/bitwise.ll is now failing as the bitwise instructions are no longer selected.



================
Comment at: lib/Target/Mips/MipsMSAInstrInfo.td:355
+
+def immi32Cst0  : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 0;}]>;
+def immi32Cst7  : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>;
----------------
This predicate is unused.


================
Comment at: lib/Target/Mips/MipsMSAInstrInfo.td:371-410
+                                               (vsplati8imm7 node:$wt)),
                                           immAllOnesV))>;
 def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
-                      (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
+                      (and node:$ws, (xor (shl vsplat_imm_eq_1,
+                                               (vsplati16imm15 node:$wt)),
                                           immAllOnesV))>;
 def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
----------------
These changes are regressing the general bitwise ISel logic for these instructions, as now their patterns are matching what the intrinsics produce when those intrinsics are lowered.

You'll probably need to duplicate the patterns instead of changing them.


https://reviews.llvm.org/D31331