[PATCH] D31965: [SLP] Enable 64-bit wide vectorization for Cyclone

[Simon Dardis via Phabricator via llvm-commits]

sdardis added inline comments.


================
Comment at: include/llvm/Analysis/TargetTransformInfoImpl.h:306
 
+  unsigned getMinVectorRegisterBitWidth() { return 128; }
+
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rengolin wrote:
> Is this value really the best default to all targets?
My quick survey of vector register widths suggests this is double the minimum.

SPARC's VIS extension uses the double precision floating point register set (64 bits wide) , as does Intel's MMX, MIPS' MIPS-3D (though currently unimplemented in LLVM).

The S/390 vector registers appear to be 128 bits, like the basic Intel SSE, MIPS MSA, ARM NEON, PowerPC Altivec.


https://reviews.llvm.org/D31965