[llvm] r299970 - Fix spelling compliment->complement. Mostly refering to 2s complement. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 11 11:47:59 PDT 2017
Author: ctopper
Date: Tue Apr 11 13:47:58 2017
New Revision: 299970
URL: http://llvm.org/viewvc/llvm-project?rev=299970&view=rev
Log:
Fix spelling compliment->complement. Mostly refering to 2s complement. NFC
Modified:
llvm/trunk/include/llvm/Transforms/IPO/FunctionAttrs.h
llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h
llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td
llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp
Modified: llvm/trunk/include/llvm/Transforms/IPO/FunctionAttrs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/IPO/FunctionAttrs.h?rev=299970&r1=299969&r2=299970&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/IPO/FunctionAttrs.h (original)
+++ llvm/trunk/include/llvm/Transforms/IPO/FunctionAttrs.h Tue Apr 11 13:47:58 2017
@@ -56,7 +56,7 @@ Pass *createPostOrderFunctionAttrsLegacy
/// This pass provides a general RPO or "top down" propagation of
/// function attributes. For a few (rare) cases, we can deduce significantly
/// more about function attributes by working in RPO, so this pass
-/// provides the compliment to the post-order pass above where the majority of
+/// provides the complement to the post-order pass above where the majority of
/// deduction is performed.
// FIXME: Currently there is no RPO CGSCC pass structure to slide into and so
// this is a boring module pass, but eventually it should be an RPO CGSCC pass
Modified: llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRInstrInfo.td?rev=299970&r1=299969&r2=299970&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.td Tue Apr 11 13:47:58 2017
@@ -694,7 +694,7 @@ Defs = [SREG] in
}
//===----------------------------------------------------------------------===//
-// One's/Two's Compliment
+// One's/Two's Complement
//===----------------------------------------------------------------------===//
let Constraints = "$src = $rd",
Defs = [SREG] in
@@ -1718,7 +1718,7 @@ Defs = [SREG] in
(implicit SREG)]>;
// CBR Rd, K
- // Alias for `ANDI Rd, COM(K)` where COM(K) is the compliment of K.
+ // Alias for `ANDI Rd, COM(K)` where COM(K) is the complement of K.
// FIXME: This uses the 'complement' encoder. We need it to also use the
// imm_ldi8 encoder. This will cause no fixups to be created on this instruction.
def CBRRdK : FRdK<0b0111,
Modified: llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h?rev=299970&r1=299969&r2=299970&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h (original)
+++ llvm/trunk/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h Tue Apr 11 13:47:58 2017
@@ -63,7 +63,7 @@ private:
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- /// Takes the compliment of a number (~0 - val).
+ /// Takes the complement of a number (~0 - val).
unsigned encodeComplement(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td?rev=299970&r1=299969&r2=299970&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td Tue Apr 11 13:47:58 2017
@@ -517,7 +517,7 @@ multiclass ADD_SUB_i1<SDNode OpNode> {
defm ADD_i1 : ADD_SUB_i1<add>;
defm SUB_i1 : ADD_SUB_i1<sub>;
-// int16, int32, and int64 signed addition. Since nvptx is 2's compliment, we
+// int16, int32, and int64 signed addition. Since nvptx is 2's complement, we
// also use these for unsigned arithmetic.
defm ADD : I3<"add.s", add>;
defm SUB : I3<"sub.s", sub>;
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp?rev=299970&r1=299969&r2=299970&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp Tue Apr 11 13:47:58 2017
@@ -902,7 +902,7 @@ bool InstCombiner::WillNotOverflowSigned
APInt RHSKnownOne(BitWidth, 0);
computeKnownBits(RHS, RHSKnownZero, RHSKnownOne, 0, &CxtI);
- // Addition of two 2's compliment numbers having opposite signs will never
+ // Addition of two 2's complement numbers having opposite signs will never
// overflow.
if ((LHSKnownOne[BitWidth - 1] && RHSKnownZero[BitWidth - 1]) ||
(LHSKnownZero[BitWidth - 1] && RHSKnownOne[BitWidth - 1]))
@@ -939,7 +939,7 @@ bool InstCombiner::WillNotOverflowSigned
APInt RHSKnownOne(BitWidth, 0);
computeKnownBits(RHS, RHSKnownZero, RHSKnownOne, 0, &CxtI);
- // Subtraction of two 2's compliment numbers having identical signs will
+ // Subtraction of two 2's complement numbers having identical signs will
// never overflow.
if ((LHSKnownOne[BitWidth - 1] && RHSKnownOne[BitWidth - 1]) ||
(LHSKnownZero[BitWidth - 1] && RHSKnownZero[BitWidth - 1]))
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