[PATCH] D28249: Improve scheduling with branch coalescing

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added a comment.

Just noticed we have a new pass in the codegen pipeline and wondered what it is about. Some comments:

- The description/examples talk about the same branch condition in the IR but the IR doesn't even have branches and this is an MI pass, not an IR pass.
- When I codegen the given example on X86 I do indeed see silly code getting generated because isel chooses a "CMOV_FR64" for each of the select instructions which "Expand ISel Pseudo-instructions" later expands into 3 if-diamonds that all have the same condition.
- It looks like we created a whole new pass to fix Expand ISel Pseudo begin stupid?
- This is a generic codegen pass but the description here indicates it only ever happens to match the patterns on PowerPC?


Repository:
  rL LLVM

https://reviews.llvm.org/D28249