[PATCH] D31911: [X86] Create the correct ADC/SBB SDNode when lowering add

[Davide Italiano via Phabricator via llvm-commits]

davide created this revision.

ADC returns two values, but we currently create an SDNode with only one. This is wrong, and when we try to combine ADC, SelectionDAG asks for the second return value, which isn't available, so we assert.

Fixes http://bugs.llvm.org/show_bug.cgi?id=32588


https://reviews.llvm.org/D31911

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/pr32588.ll


Index: test/CodeGen/X86/pr32588.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/pr32588.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
+
+ at c = external local_unnamed_addr global i32, align 4
+ at b = external local_unnamed_addr global i32, align 4
+ at d = external local_unnamed_addr global i32, align 4
+
+; CHECK: cmpl    $1, c(%rip)
+; CHECK-NEXT: sbbl    %eax, %eax
+; CHECK-NEXT: andl    $1, %eax
+; CHECK-NEXT: movl    %eax, d(%rip)
+; CHECK-NEXT: retq
+
+define void @fn1() {
+entry:
+  %0 = load i32, i32* @c, align 4
+  %tobool1 = icmp eq i32 %0, 0
+  %xor = zext i1 %tobool1 to i32
+  %1 = load i32, i32* @b, align 4
+  %tobool2 = icmp ne i32 %1, 0
+  %tobool4 = icmp ne i32 undef, 0
+  %2 = and i1 %tobool4, %tobool2
+  %sub = sext i1 %2 to i32
+  %div = sdiv i32 %sub, 2
+  %add = add nsw i32 %div, %xor
+  store i32 %add, i32* @d, align 4
+  ret void
+}
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -34606,15 +34606,17 @@
   SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, Z,
                                DAG.getConstant(1, DL, Z.getValueType()));
 
+  SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
+
   // X - (Z != 0) --> sub X, (zext(setne Z, 0)) --> adc X, -1, (cmp Z, 1)
   // X + (Z != 0) --> add X, (zext(setne Z, 0)) --> sbb X, -1, (cmp Z, 1)
   if (CC == X86::COND_NE)
-    return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, VT, X,
+    return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, VTs, X,
                        DAG.getConstant(-1ULL, DL, VT), NewCmp);
 
   // X - (Z == 0) --> sub X, (zext(sete  Z, 0)) --> sbb X, 0, (cmp Z, 1)
   // X + (Z == 0) --> add X, (zext(sete  Z, 0)) --> adc X, 0, (cmp Z, 1)
-  return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, VT, X,
+  return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, VTs, X,
                      DAG.getConstant(0, DL, VT), NewCmp);
 }
 


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