[PATCH] D31872: AMDGPU: Minor SReg64 register class refactoring

[Konstantin Zhuravlyov via Phabricator via llvm-commits]

kzhuravl added a comment.

In https://reviews.llvm.org/D31872#722575, @arsenm wrote:

> I think this requires changing the register class for SSrc_32/VSrc_32 to be the one that includes the special 32-bit regs. I think I started doing this to start supporting vccz and the other special 1-bit inputs


I do not think so. src_*_base and src_*_limit are 64 bit inline constants. Here is an example of src_shared_base:

  {SMB.shared_base[15:0], 48’h000000000000}

src_*_base and src_*_limit also do not have subregisters.



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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:133
 
+def APERTURE_CLASS : RegisterClass<"AMDGPU", [i64], 32,
+  (add SRC_SHARED_BASE, SRC_SHARED_LIMIT, SRC_PRIVATE_BASE,
----------------
arsenm wrote:
> Aren't these 32bit only, so i32?
Aperture registers are 64 bit inline constants.


================
Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:306
 
-def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
+def SReg_64_WITH_SUBREGS : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
   (add SReg_64_XEXEC, EXEC)> {
----------------
arsenm wrote:
> It would be less annoying to keep this with the same name and to rename the other one
Which one?


================
Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:313
+def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
+  (add SReg_64_WITH_SUBREGS, APERTURE_CLASS)> {
+  let CopyCost = 1;
----------------
arsenm wrote:
> This is adding 32-bit registers to the 64-bit register class?
Those are 64 bit inline constants, hence in 64 bit register class.


================
Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:315
+  let CopyCost = 1;
+  let AllocationPriority = 8;
+}
----------------
arsenm wrote:
> The set with the aperture regs should be unallocatable
`APERTURE_REGS` is `let isAllocatable = 0`.


https://reviews.llvm.org/D31872