[PATCH] D31833: [x86] Relax the check in areLoadsFromSameBasePtr

[Easwaran Raman via Phabricator via llvm-commits]

eraman created this revision.

The code returns false if the Scale value (which should match in Load1 and Load2) is not 1. I think all that is required is every operand except the displacement must be identical.


https://reviews.llvm.org/D31833

Files:
  lib/Target/X86/X86InstrInfo.cpp
  test/CodeGen/X86/load-slice.ll


Index: test/CodeGen/X86/load-slice.ll
===================================================================
--- test/CodeGen/X86/load-slice.ll
+++ test/CodeGen/X86/load-slice.ll
@@ -19,10 +19,10 @@
 ; STRESS-LABEL: t1:
 ; Load out[out_start + 8].real, this is base + 8 * 8 + 0.
 ; STRESS: vmovss 64([[BASE:[^(]+]]), [[OUT_Real:%xmm[0-9]+]]
-; Add low slice: out[out_start].real, this is base + 0.
-; STRESS-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]]
 ; Load out[out_start + 8].imm, this is base + 8 * 8 + 4.
 ; STRESS-NEXT: vmovss 68([[BASE]]), [[OUT_Imm:%xmm[0-9]+]]
+; Add low slice: out[out_start].real, this is base + 0.
+; STRESS-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]]
 ; Add high slice: out[out_start].imm, this is base + 4.
 ; STRESS-NEXT: vaddss 4([[BASE]]), [[OUT_Imm]], [[RES_Imm:%xmm[0-9]+]]
 ; Swap Imm and Real.
@@ -34,10 +34,10 @@
 ; REGULAR-LABEL: t1:
 ; Load out[out_start + 8].real, this is base + 8 * 8 + 0.
 ; REGULAR: vmovss 64([[BASE:[^)]+]]), [[OUT_Real:%xmm[0-9]+]]
-; Add low slice: out[out_start].real, this is base + 0.
-; REGULAR-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]]
 ; Load out[out_start + 8].imm, this is base + 8 * 8 + 4.
 ; REGULAR-NEXT: vmovss 68([[BASE]]), [[OUT_Imm:%xmm[0-9]+]]
+; Add low slice: out[out_start].real, this is base + 0.
+; REGULAR-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]]
 ; Add high slice: out[out_start].imm, this is base + 4.
 ; REGULAR-NEXT: vaddss 4([[BASE]]), [[OUT_Imm]], [[RES_Imm:%xmm[0-9]+]]
 ; Swap Imm and Real.
Index: lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- lib/Target/X86/X86InstrInfo.cpp
+++ lib/Target/X86/X86InstrInfo.cpp
@@ -8980,26 +8980,20 @@
     break;
   }
 
-  // Check if chain operands and base addresses match.
+  // All operands except the displacement should match.
   if (Load1->getOperand(0) != Load2->getOperand(0) ||
+      Load1->getOperand(1) != Load2->getOperand(1) ||
+      Load1->getOperand(2) != Load2->getOperand(2) ||
+      Load1->getOperand(4) != Load2->getOperand(4) ||
       Load1->getOperand(5) != Load2->getOperand(5))
     return false;
-  // Segment operands should match as well.
-  if (Load1->getOperand(4) != Load2->getOperand(4))
-    return false;
-  // Scale should be 1, Index should be Reg0.
-  if (Load1->getOperand(1) == Load2->getOperand(1) &&
-      Load1->getOperand(2) == Load2->getOperand(2)) {
-    if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
-      return false;
 
-    // Now let's examine the displacements.
-    if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
-        isa<ConstantSDNode>(Load2->getOperand(3))) {
-      Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
-      Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
-      return true;
-    }
+  // Now let's examine if the displacements are constants.
+  if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
+      isa<ConstantSDNode>(Load2->getOperand(3))) {
+    Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
+    Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
+    return true;
   }
   return false;
 }


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