[PATCH] D31872: AMDGPU: Minor SReg64 register class refactoring

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:133
 
+def APERTURE_CLASS : RegisterClass<"AMDGPU", [i64], 32,
+  (add SRC_SHARED_BASE, SRC_SHARED_LIMIT, SRC_PRIVATE_BASE,
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Aren't these 32bit only, so i32?


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:306
 
-def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
+def SReg_64_WITH_SUBREGS : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
   (add SReg_64_XEXEC, EXEC)> {
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It would be less annoying to keep this with the same name and to rename the other one


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:313
+def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
+  (add SReg_64_WITH_SUBREGS, APERTURE_CLASS)> {
+  let CopyCost = 1;
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This is adding 32-bit registers to the 64-bit register class?


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:315
+  let CopyCost = 1;
+  let AllocationPriority = 8;
+}
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The set with the aperture regs should be unallocatable


https://reviews.llvm.org/D31872